added trigger to ecal prescale

ecal/addr_table/eprocessor.xml

@@ -8,6 +8,7 @@
       <node id="data_streaming_lat" mask="0x001e000" description="data streaming latency."/>  
       <node id="n_pre"              mask="0x01e0000" description="number of bx data to take before trigger"/>  
       <node id="n_post"             mask="0x1e00000" description="number of bx data to take after trigger"/>  
+      <node id="n_trig_prescale"    mask="0x1e00000" description="number of prescale of trigger"/>  
     </node>
     <node id="stat" address="0x1" description="status">
       <node id="block_latency"   mask="0x1ff" description="latency"/>

ecal/firmware/hdl/EcalDataProcessor.vhd

@@ -46,6 +46,7 @@ architecture rtl of EcalDataProcessor is
   signal n_pre                   : std_logic_vector(3 downto 0);
   signal n_post                  : std_logic_vector(3 downto 0);
   signal n_data_out              : integer range 1 to 8 := 1;
+  signal n_trig_prescale         : integer range 0 to 127 := 0;
 
   -- 448 length data with valid(1 clock at 320MHz when the data changes at 40MHz)
   signal data_start                   : std_logic;
@@ -157,6 +158,7 @@ begin
   n_pre              <= ctrl_regs(0)(20 downto 17);
   n_post             <= ctrl_regs(0)(24 downto 21);
   n_data_out         <= to_integer(unsigned(n_pre) + unsigned(n_post)) + 1;
+  n_trig_prescale    <= ctrl_regs(0)(31 downto 25);
 
   stat_regs(0)(8 downto 0) <= std_logic_vector(ttrig_block_lat_s);
   stat_regs(0)(9) <= data_ram_ena;
@@ -244,6 +246,8 @@ begin
     constant bit_last  : integer := 66;
     constant bit_ofst : integer := 67;
 
+    variable trig_read_count : integer range 0 to 127 := 0;
+
     begin
   
         if reset = '1' then
@@ -277,6 +281,7 @@ begin
           data_ram_addrb <= (others => '0');
           timer := 0;
           o_timer := 0;
+          trig_read_count := 0;
 
         elsif rising_edge(clk_p) then
 
@@ -327,9 +332,13 @@ begin
           if data_ram_doutb(bit_start) = '1' then -- data bit_start = '1' is synchronized with the trig_ready by the raddr arrangement
             o_timer := 0;
             if trig_ready_d = '1' then
-              trig_valid := trig_en_d;
-              data_out_count := 0;
-              trig_start := '1';
+              trig_read_count := trig_read_count + 1;
+              if trig_read_count = n_trig_prescale then
+                trig_valid := trig_en_d;
+                data_out_count := 0;
+                trig_start := '1';
+                trig_read_count := 0;
+              end if;
             elsif trig_en_d = '1' then
               data_out_count := data_out_count + 1;
               if data_out_count = n_data_out then