Update top/addr_table/emp_payload.xml, top/firmware/hdl/emp_payload.vhd,...

Update top/addr_table/emp_payload.xml, top/firmware/hdl/emp_payload.vhd, top/firmware/hdl/LinkCombiner.vhd files

top/addr_table/emp_payload.xml

@@ -27,6 +27,8 @@
             <node id="link_combiner" mask="0xff0"/>
             <node id="head_start_select" mask="0x3000"/>
         </node>
+        <node id="header_user_bits" address="0x3"/>
+        
         <node id="super_id" address="0x4"/>
         <node id="lff" address="0x5" mask="0x0001"/>
         <node id="link_combiner_fifo" address="0x6">

top/firmware/hdl/LinkCombiner.vhd

@@ -14,19 +14,20 @@ entity LinkCombiner is
     );
     port (
         --- Input Ports ---
-        clk_p        : in std_logic;
-        reset        : in std_logic;
-        output_reset : in std_logic := '0';
-        output_rd_en : in std_logic_vector(N_OUTPUT_LINKS - 1 downto 0) := (others => '0');
-        links_in     : in ldata(N_INPUT_LINKS - 1 downto 0);
-        packet_start : in std_logic;
-        header_in    : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+        clk_p            : in std_logic;
+        reset            : in std_logic;
+        output_reset     : in std_logic := '0';
+        output_rd_en     : in std_logic_vector(N_OUTPUT_LINKS - 1 downto 0) := (others => '0');
+        links_in         : in ldata(N_INPUT_LINKS - 1 downto 0);
+        packet_start     : in std_logic;
+        header_in        : in tCICHeaderArray(cNumberOfFEModules * cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+        header_user_bits : in std_logic_vector(31 downto 0) := (others => '0');
         --- Ouput Ports ---
-        links_out    : out ldata(N_OUTPUT_LINKS - 1 downto 0);
+        links_out        : out ldata(N_OUTPUT_LINKS - 1 downto 0);
         --- Debug Ports ---
-        debug          : out lword := LWORD_NULL;
-        debug_super_id : out std_logic_vector(31 downto 0);
-        debug_fifo     : out std_logic_vector(31 downto 0) := (others => '0')
+        debug            : out lword := LWORD_NULL;
+        debug_super_id   : out std_logic_vector(31 downto 0);
+        debug_fifo       : out std_logic_vector(31 downto 0) := (others => '0')
     );
 end LinkCombiner;
 
@@ -330,7 +331,7 @@ begin
             
             if counter = 1 then
                 output_wr_en_array_buf(0)             <= '1';
-                output_din_array_buf(0)(63 downto 32) <= X"DEADBEEF";
+                output_din_array_buf(0)(63 downto 32) <= header_user_bits;
                 output_din_array_buf(0)(31 downto 0)  <= std_logic_vector(super_id);
             elsif counter = 2 then
                 output_din_array_buf(0) <= (others => '0');

top/firmware/hdl/emp_payload.vhd

@@ -75,7 +75,7 @@ constant input_width           : integer := 9;
 signal status_registers        : ipb_reg_v(N_STAT_HIST - 1 downto 0) := (others => (others => '0'));
 signal control_registers       : ipb_reg_v(N_CTRL_HIST - 1 downto 0) := (others => (others => '0'));
 signal link_aggregator_status_registers        : ipb_reg_v(4 - 1 downto 0) := (others => (others => '0'));
-signal link_aggregator_control_registers       : ipb_reg_v(3 - 1 downto 0) := (others => (others => '0'));
+signal link_aggregator_control_registers       : ipb_reg_v(4 - 1 downto 0) := (others => (others => '0'));
 
 signal trigger_window_lower    : std_logic_vector(31 downto 0)            := (others => '0');
 signal trigger_window_upper    : std_logic_vector(3 downto 0)             := (others => '0');
@@ -417,7 +417,7 @@ packet_start <= header_start_array(to_integer(unsigned(link_aggregator_control_r
 LinkAggregatorControlInstance: entity work.ipbus_ctrlreg_v
 --==============================--
 generic map(
-    N_CTRL       => 3,
+    N_CTRL       => 4,
     N_STAT       => 4
 )
 port map(
@@ -438,19 +438,20 @@ generic map (
 )
 port map (
     --- Input Ports ---
-    clk_p        => clk_p,
-    reset        => readout_reset,
-    output_reset => link_aggregator_control_registers(1)(0),
-    output_rd_en => link_combiner_rd_en,
-    links_in     => link_combiner_input,
-    packet_start => packet_start,
-    header_in    => header_array,
+    clk_p            => clk_p,
+    reset            => readout_reset,
+    output_reset     => link_aggregator_control_registers(1)(0),
+    output_rd_en     => link_combiner_rd_en,
+    links_in         => link_combiner_input,
+    packet_start     => packet_start,
+    header_in        => header_array,
+    header_user_bits => link_aggregator_control_registers(3),
     --- Output Ports ---
-    links_out    => eth_link_out,
+    links_out        => eth_link_out,
     --- Debug Ports ---
-    debug          => link_combiner_debug,
-    debug_super_id => link_combiner_debug_super_id,
-    debug_fifo     => link_aggregator_status_registers(2)
+    debug            => link_combiner_debug,
+    debug_super_id   => link_combiner_debug_super_id,
+    debug_fifo       => link_aggregator_status_registers(2)
 );
 
 q(32).valid  <= eth_link_out(0).valid;