Update top/firmware/hdl/emp_payload.vhd

top/firmware/hdl/emp_payload.vhd

@@ -248,17 +248,24 @@ end generate;
 --==============================--
 genDebugging: for i in 0 to cNumberOfFEModules - 1 generate
 --==============================--
+    signal data_in_cache : std_logic_vector(63 downto 0) := (others => '0');
 begin
-    q(20+i).valid <= d(cDTCInputLinkMap(i)).valid;
-    q(20+i).data <= d(cDTCInputLinkMap(i)).data;
-    q(20+i).start <= '1';
-    q(20+i).strobe <= '1';
-
-    q(24+i).start <= '1';
-    q(24+i).strobe <= '1';
-    q(24+i).valid <= stubs(i).valid;
-    q(24+i).data(55 downto 0) <= stubs(i).data(55 downto 0);
-    q(24+i).data(57 downto 56) <= header_start_array(i);
+    pRegisterInput : process(clk_p)
+    begin
+        if rising_edge(clk_p) then
+            data_in_cache <= d(cDTCInputLinkMap(i)).data;
+            q(20+i).valid <= '1';
+            q(20+i).data <= data_in_cache;
+            q(20+i).start <= '1';
+            q(20+i).strobe <= '1';
+
+            q(24+i).start <= '1';
+            q(24+i).strobe <= '1';
+            q(24+i).valid <= stubs(i).valid;
+            q(24+i).data(55 downto 0) <= stubs(i).data(55 downto 0);
+            q(24+i).data(57 downto 56) <= header_start_array(i);
+        end if;
+    end process pRegisterInput;
 end generate genDebugging;