Initial commit

dependencies.yml

@@ -45,7 +45,7 @@ sources:
         url: https://gitlab.cern.ch/gbtsc-fpga-support/gbt-sc.git
 
     dtc:
-        branch: master
+        branch: feature/heterogeneous-dtc
         url: https://gitlab.cern.ch/cms-tracker-phase2-data-processing/BE_firmware/dtc.git
 
     dtc-stub-processing:

top/firmware/cfg/top.dep

 include -c histogram:top histogram.dep
-include -c dtc:dtc-fe/2S/5G-FEC12 module.dep
-include -c dtc:dtc-fe/2S/5G-FEC12 framer.dep
+include -c dtc:dtc-fe common.dep
+include -c dtc:dtc-fe framers.dep
 include -c dtc:dtc-be/common daqpath.dep
 include -c dtc:dtc-be/common common.dep
 include -c dtc-stub-processing:common tools.dep

top/firmware/hdl/emp_payload.vhd

@@ -205,17 +205,17 @@ begin
         LinkInterfaceInstance : entity work.LinkInterface
         --==============================--
         generic map (
-            module_type => "2S"
+            module_type => cDTCInputLinkMap(i).module_type
         )
         port map (
             --- Input Ports ---
             clk_p               => clk_p,
             clk40               => clk40,
-            link_in             => d(cDTCInputLinkMap(i)),
+            link_in             => d(cDTCInputLinkMap(i).index),
             daq_read            => daq_read(i),
             global_fcmd         => global_fcmd,
             --- Output Ports ---
-            link_out            => q(cDTCInputLinkMap(i)),
+            link_out            => q(cDTCInputLinkMap(i).index),
             stub_out            => stubs(i),
             header_out          => header_array(cNumberOfCICs * i + cNumberOfCICs - 1 downto cNumberOfCICs * i),
             daq_out             => daq_data(i),

top/firmware/hdl/link_maps.vhd

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
+use work.dtc_link_maps_func.all;
 
 package dtc_link_maps is
+
     constant cNumberOfFEModules   : integer := 4;
     constant cNumberOfOutputLinks : integer := 4;
 
-    type tDTCInputLinkMap is array(0 to cNumberOfFEModules - 1) of integer;
-    constant cDTCInputLinkMap     : tDTCInputLinkMap := (8, 9, 10, 11);
+    type tDTCInputLinkMap is array(0 to cNumberOfFEModules - 1) of tDTCInputLinkConfig;
+    constant cDTCInputLinkMap     : tDTCInputLinkMap := (
+        0 => (8,  "2S", "CIC2"),
+        1 => (9,  "2S", "CIC2"),
+        2 => (10, "2S", "CIC2"),
+        3 => (11, "2S", "CIC2")
+    );
 
     type tDTCOutputLinkMap is array(0 to cNumberOfOutputLinks - 1) of integer;
-    constant cDTCOutputLinkMap    : tDTCOutputLinkMap := (16, 17, 18, 19);
+    constant cDTCOutputLinkMap    : tDTCOutputLinkMap := (
+        16, 17, 18, 19
+    );
+
+    function selectModuleTypeFromChannel(channel : in integer) return string;
 end package dtc_link_maps;
+
+package body dtc_link_maps is
+
+    function selectModuleTypeFromChannel(channel : in integer) return string is
+    begin
+        for i in 0 to cDTCInputLinkMap'length - 1 loop
+            if cDTCInputLinkMap(i).index = channel then
+                return cDTCInputLinkMap(i).module_type;
+            end if;
+        end loop;
+    end selectModuleTypeFromChannel;
+
+end package body dtc_link_maps;