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Commit e3a9e02f authored by David Gabriel Monk's avatar David Gabriel Monk
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Merge branch 'dmonk-master-patch-5bd8' into 'master'

Update to new DTC version

See merge request !46
parents 638d3f53 3aba8ffc
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1 merge request!46Update to new DTC version
Pipeline #7388421 passed
...@@ -128,11 +128,11 @@ begin ...@@ -128,11 +128,11 @@ begin
-- Infrastructure -- Infrastructure
pcie_rst_invert : if emp_slim_top_decl.PCIE_RST_ACTIVE_LEVEL = '1' generate pcie_rst_invert : if emp_slim_top_decl.PCIE_RST_ACTIVE_LEVEL = '1' generate
pcie_sys_rst_n <= not pcie_sys_rst; pcie_sys_rst_n <= not pcie_sys_rst;
else generate -- pcie_rst_invert else generate -- pcie_rst_invert
pcie_sys_rst_n <= pcie_sys_rst; pcie_sys_rst_n <= pcie_sys_rst;
end generate pcie_rst_invert; end generate pcie_rst_invert;
infra : entity work.emp_infra_pcie infra : entity work.emp_infra_pcie
port map( port map(
...@@ -274,7 +274,7 @@ end generate pcie_rst_invert; ...@@ -274,7 +274,7 @@ end generate pcie_rst_invert;
rst => ipb_rst, rst => ipb_rst,
ipb_in => ipb_w_array(N_SLV_PAYLOAD), ipb_in => ipb_w_array(N_SLV_PAYLOAD),
ipb_out => ipb_r_array(N_SLV_PAYLOAD), ipb_out => ipb_r_array(N_SLV_PAYLOAD),
clk40 => clk40, clk40 => clk40,
clk_payload => clks_aux, clk_payload => clks_aux,
rst_payload => rsts_aux, rst_payload => rsts_aux,
clk_p => clk_p, clk_p => clk_p,
...@@ -292,33 +292,33 @@ end generate pcie_rst_invert; ...@@ -292,33 +292,33 @@ end generate pcie_rst_invert;
-- 10g -- 10g
gbe_q => gbe_ldata, gbe_q => gbe_ldata,
gbe_backpressure => gbe_backpressure gbe_backpressure => gbe_backpressure
); );
slink_check : if slink_quads_enabled(SLINK_CONF) > 0 generate slink_check : if slink_quads_enabled(SLINK_CONF) > 0 generate
slink : entity work.emp_slink_interface slink : entity work.emp_slink_interface
generic map ( generic map (
throughput => SLINK_THROUGHPUT, throughput => SLINK_THROUGHPUT,
technology => SLINK_XCVR_TYPE, technology => SLINK_XCVR_TYPE,
ref_clock_freq => SLINK_REFCLK_FREQ, ref_clock_freq => SLINK_REFCLK_FREQ,
ref_clock_index => IO_REGION_SPEC(SLINK_CONF(0).region).io_async_refclk ref_clock_index => IO_REGION_SPEC(SLINK_CONF(0).region).io_async_refclk
) )
port map ( port map (
ipb_clk => ipb_clk, ipb_clk => ipb_clk,
ipb_rst => ipb_rst, ipb_rst => ipb_rst,
ipb_in => ipb_w_array(N_SLV_SLINK), ipb_in => ipb_w_array(N_SLV_SLINK),
ipb_out => ipb_r_array(N_SLV_SLINK), ipb_out => ipb_r_array(N_SLV_SLINK),
clk_40 => clk40ish, clk_40 => clk40ish,
clk_p => clk_p, clk_p => clk_p,
slink_d => slink_payload_data, slink_d => slink_payload_data,
backpressure => slink_backpressure, backpressure => slink_backpressure,
refclkp => refclkp, refclkp => refclkp,
refclkn => refclkn refclkn => refclkn
); );
end generate; end generate;
-- --
-- 10g -- 10g
......
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