Skip to content
Snippets Groups Projects
Commit f1cedbc9 authored by Marco Riggirello's avatar Marco Riggirello
Browse files

LinkAggregatorCore bug fix

parent 4b95d70b
No related branches found
No related tags found
2 merge requests!405 bits thresholds registers,!35Added configurable threshold for each input link
Pipeline #6150292 failed
Stage: Static Analysis
Stage: Make Project
Stage: Pre-build Checks
Stage: Synthesis
Stage: Implementation
Stage: Package
Stage: Upload to Registry
Show whitespace changes
Inline Side-by-side
common/firmware/hdl/LinkAggregatorCore.vhd
+ 1
− 1
View file @ f1cedbc9
...@@ -231,7 +231,7 @@ begin ...@@ -231,7 +231,7 @@ begin
begin begin
if rising_edge(clk_p) then if rising_edge(clk_p) then
if packet_start_buffered = '1' then if packet_start_buffered = '1' then
if unsigned(count_cache) >= thresholds_l(i) and (unsigned(count_cache) <= thresholds_u(i) or thresholds_u(i) = "0000") then if unsigned(count_cache) >= thresholds_l(i) and (unsigned(count_cache) <= thresholds_u(i) or to_integer(unsigned(thresholds_u(i))) = 0) then
bx_valid_array(N_LINKS*j + i) <= '1'; bx_valid_array(N_LINKS*j + i) <= '1';
else else
bx_valid_array(N_LINKS*j + i) <= '0'; bx_valid_array(N_LINKS*j + i) <= '0';
... ...
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please to comment