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Update file LinkCombinerCore.vhd

Merged Update file LinkCombinerCore.vhd
feature/improved-link-combiner into heterogeneous-dtc
Merged David Gabriel Monk requested to merge feature/improved-link-combiner into heterogeneous-dtc
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common/firmware/hdl/LinkCombinerCore.vhd
+ 28
− 27
@@ -5,6 +5,7 @@ use work.emp_data_types.all;
use work.dtc_link_maps.all;
use work.dtc_constants.all;
use work.dtc_data_types.all;
use IEEE.std_logic_misc.all;
entity LinkCombinerCore is
@@ -87,7 +88,12 @@ architecture Behavioral of LinkCombinerCore is
constant cNullValidArray : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
constant cFullEmptyArray : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '1');
-- Signals
-- Signals
signal input_links_valid : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
signal all_input_links_valid : std_logic := '0';
signal all_input_links_valid_previous : std_logic := '0';
signal start_output : std_logic := '0';
signal input_dout_array : tWordArray(0 to N_INPUT_LINKS - 1) := (others => (others => '0'));
signal input_rd_en_array : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
signal input_almost_empty_array, input_valid_array : std_logic_vector(N_INPUT_LINKS - 1 downto 0) := (others => '0');
@@ -113,7 +119,6 @@ architecture Behavioral of LinkCombinerCore is
signal output_rd_en : std_logic := '0';
signal counter : integer := 0;
signal status_sr : tStatusShiftRegister := (others => (others => '0'));
signal bcid_sr : tBCIDShiftRegister := (others => (others => '0'));
signal super_id : unsigned(32 - 1 downto 0) := (others => '0');
@@ -124,6 +129,7 @@ architecture Behavioral of LinkCombinerCore is
begin
--==============================--
genInputLinkBuffers : for i in 0 to N_INPUT_LINKS - 1 generate
--==============================--
@@ -132,6 +138,8 @@ begin
signal wr_en : std_logic := '0';
begin
input_links_valid(i) <= links_in(i).valid;
--==============================--
InputLinkBufferInstance : link_agg_all_links_fifo
--==============================--
@@ -246,13 +254,21 @@ begin
--==============================--
begin
if rising_edge(clk_p) then
if packet_start = '1' then
if start_output = '1' then
input_data_valid <= '1';
else
if reset = '1' then
input_data_valid <= '0';
end if;
end if;
all_input_links_valid <= and_reduce(input_links_valid);
all_input_links_valid_previous <= all_input_links_valid;
if all_input_links_valid = '0' and all_input_links_valid_previous = '1' then
start_output <= '1';
else
start_output <= '0';
end if;
end if;
end process pValidDataChecker;
@@ -266,7 +282,7 @@ begin
begin
if rising_edge(clk_p) then
-- Iterate pointer to successively empty the input FIFOs
if input_data_valid = '1' and counter = 4 then
if input_data_valid = '1' and counter = 3 then
if input_almost_empty_array(output_pointer) = '0' then
input_rd_en_array(output_pointer) <= '1';
else
@@ -284,14 +300,16 @@ begin
end if;
end if;
else
output_pointer <= 0;
next_pointer_location := 0;
input_rd_en_array(output_pointer) <= '0';
end if;
-- Packet control bits logic
if packet_start = '1' then
if start_output = '1' then
counter <= 0;
else
if counter < 4 then
if counter < 3 then
counter <= counter + 1;
else
counter <= counter;
@@ -299,7 +317,7 @@ begin
end if;
output_pointer_buffered <= output_pointer;
output_din <= input_dout_array(output_pointer_buffered);
output_wr_en <= input_valid_array(output_pointer_buffered);
output_wr_en <= input_valid_array(output_pointer_buffered) and (not reset);
if reset = '1' then
@@ -323,22 +341,11 @@ begin
output_din_buf(31 downto 0) <= std_logic_vector(super_id);
elsif counter = 2 then
output_din_buf <= (others => '0');
output_din_buf(63 downto 56) <= std_logic_vector(packet_stub_count_previous);
output_din_buf(47 downto 36) <= bcid_sr(bcid_sr'high);
output_din_buf(11 downto 0) <= bcid_sr(bcid_sr'high);
output_din_buf(19 downto 12) <= std_logic_vector(packet_stub_count_previous);
output_wr_en_buf <= '1';
if cNumberOfFEModules < 3 then
output_din_buf(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high);
else
output_din_buf(2 * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high)(2 * cNumberOfCICs * 9 - 1 downto 0);
end if;
elsif counter = 3 then
output_din_buf <= (others => '0');
output_wr_en_buf <= '1';
if cNumberOfFEModules >= 3 and cNumberOfFEModules < 6 then
output_din_buf((cNumberOfFEModules - 2) * cNumberOfCICs * 9 - 1 downto 0) <= status_sr(status_sr'high)(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 2 * cNumberOfCICs * 9);
end if;
else
output_wr_en_buf <= output_wr_en;
output_wr_en_buf <= output_wr_en and (not reset);
output_din_buf <= output_din;
end if;
@@ -349,7 +356,6 @@ begin
--==============================--
pBufferHeader: process(clk_p)
--==============================--
variable status : std_logic_vector(cNumberOfFEModules * cNumberOfCICs * 9 - 1 downto 0) := (others => '0');
variable bcid : std_logic_vector(12 - 1 downto 0) := (others => '0');
begin
if rising_edge(clk_p) then
@@ -357,11 +363,6 @@ begin
super_id <= (others => '0');
else
if packet_start = '1' then
for i in cNumberOfFEModules - 1 downto 0 loop
status(i*cNumberOfCICs*9 + 8 downto i*cNumberOfCICs*9) := std_logic_vector(header_in(i*cNumberOfCICs).status);
status(i*cNumberOfCICs*9 + 17 downto i*cNumberOfCICs*9 + 9) := std_logic_vector(header_in(i*cNumberOfCICs + 1).status);
end loop;
status_sr <= status_sr(status_sr'high - 1 downto 0) & status;
bcid := std_logic_vector(header_in(0).bcid);
bcid_sr <= bcid_sr(bcid_sr'high - 1 downto 0) & bcid;
if unsigned(bcid_sr(bcid_sr'high)) > unsigned(bcid_sr(bcid_sr'high - 1)) then