Update to new DTC version

replacements/emp-fwk/components/top/firmware/hdl/emp_top_pcie_both_ttc.vhd

@@ -128,11 +128,11 @@ begin
 
 -- Infrastructure
 
-pcie_rst_invert : if emp_slim_top_decl.PCIE_RST_ACTIVE_LEVEL = '1' generate
-pcie_sys_rst_n <= not pcie_sys_rst;
-else generate -- pcie_rst_invert
-pcie_sys_rst_n <= pcie_sys_rst;  
-end generate pcie_rst_invert;
+  pcie_rst_invert : if emp_slim_top_decl.PCIE_RST_ACTIVE_LEVEL = '1' generate
+    pcie_sys_rst_n <= not pcie_sys_rst;
+  else generate -- pcie_rst_invert
+    pcie_sys_rst_n <= pcie_sys_rst;  
+  end generate pcie_rst_invert;
 
   infra : entity work.emp_infra_pcie
     port map(
@@ -274,7 +274,7 @@ end generate pcie_rst_invert;
       rst           => ipb_rst,
       ipb_in        => ipb_w_array(N_SLV_PAYLOAD),
       ipb_out       => ipb_r_array(N_SLV_PAYLOAD),
-      clk40         => clk40,	        
+      clk40         => clk40,
       clk_payload   => clks_aux,
       rst_payload   => rsts_aux,
       clk_p         => clk_p,
@@ -292,33 +292,33 @@ end generate pcie_rst_invert;
       -- 10g
       gbe_q             => gbe_ldata,
       gbe_backpressure  => gbe_backpressure
-    );
+      );
 
-    slink_check : if slink_quads_enabled(SLINK_CONF) > 0 generate
-      slink : entity work.emp_slink_interface
-        generic map (
-          throughput      => SLINK_THROUGHPUT,
-          technology      => SLINK_XCVR_TYPE,
-          ref_clock_freq  => SLINK_REFCLK_FREQ,
-          ref_clock_index => IO_REGION_SPEC(SLINK_CONF(0).region).io_async_refclk
+  slink_check : if slink_quads_enabled(SLINK_CONF) > 0 generate
+    slink : entity work.emp_slink_interface
+      generic map (
+        throughput      => SLINK_THROUGHPUT,
+        technology      => SLINK_XCVR_TYPE,
+        ref_clock_freq  => SLINK_REFCLK_FREQ,
+        ref_clock_index => IO_REGION_SPEC(SLINK_CONF(0).region).io_async_refclk
         )
-        port map (
-          ipb_clk      => ipb_clk,
-          ipb_rst      => ipb_rst,
-          ipb_in       => ipb_w_array(N_SLV_SLINK),
-          ipb_out      => ipb_r_array(N_SLV_SLINK),
+      port map (
+        ipb_clk      => ipb_clk,
+        ipb_rst      => ipb_rst,
+        ipb_in       => ipb_w_array(N_SLV_SLINK),
+        ipb_out      => ipb_r_array(N_SLV_SLINK),
 
-          clk_40       => clk40ish,
-          clk_p        => clk_p,
+        clk_40       => clk40ish,
+        clk_p        => clk_p,
 
-          slink_d      => slink_payload_data,
-          backpressure => slink_backpressure,
+        slink_d      => slink_payload_data,
+        backpressure => slink_backpressure,
 
-          refclkp      => refclkp,
-          refclkn      => refclkn
+        refclkp      => refclkp,
+        refclkn      => refclkn
         );
   end generate;
-
+  
 
   --
   -- 10g