Latency scans

Summary

This is a split of #5 for internal latency scans. The intent is to come to a specification that can be implemented.

Initial description

This is what I inferred from @anlevin's description in #5. It may be incorrect.

The internal latency scan determines which entry in the VFAT3 internal buffer should be fetched when a L1A is received. Data is generated by pulsing the VFAT (one channel only? all channels?) at some rate (what's the value?). Every pulse is set to last 4 bunch crossings (why?). L1A's are sent back for every L1 trigger sent by the VFAT, and the data stored in the VFAT buffer at the value of the Latency register (what's the real name?) are sent back to the AMC and stored to disk.

The procedure is repeated for every possible value of the Latency register. The correct value of the Latency can be inferred from a number-of-hits-seen vs latency histogram like this:

The plateau is 4 bins wide because every bin corresponds to possible value of the Latency, which is specified as a number of bunch crossings, and the pulse is kept high for 4 bunch crossings. The first bin with a large number of hits corresponds to the "best" latency setting.

Corner cases

The plateau above is not sharp. This creates an ambiguity for the best value of the latency: it can be the bin at 31 or the bin at 32.