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Reload the backend firmware and check for reset completion

Laurent Petre requested to merge feature/reset-and-programming-checks into develop


This MR aims at fixing the random slow control communication issues with the OH and VFAT. It was observed that during clock changes, the Virtex-7 firmware can end up in a fuzzy state in which it is stuck until reloaded. In order to prevent such problem, the backend Virtex-7 is now reloaded during the initialization transition (should use the backend local clock) and the configuration transition (should use the stable external TTC clock).

In addition, every reset operation is now checked for correct completion.

Related Issue

How Has This Been Tested?

Many runs were successfully launched on the b904 integration setup. Larger scale tests are pending at p5.

Types of changes

  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)


  • My code follows the code style of this project.
  • My change requires a change to the documentation.
  • I have updated the documentation accordingly.
  • I have read the CONTRIBUTING document.
  • I have added tests to cover my changes.
  • All new and existing tests passed.

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