This MR adds a phase scan for the FPGA slow control e-link. For each phase from 0 to 15 the scan sends many times (by default 50 times) a signal through the e-link by writing the register
BEFE.GEM.OH.OH*.FPGA.CONTROL.LOOPBACK.DATA and reads the loopback value from the same register. If the read value is different from the written one, the phase is marked as bad.
The raw and analysed results are saved in
/tmp/gemdata/fpgaSlowControlPhaseScan/. The analysed result contains the optimal phase determined in the window of good phases.
This MR addresses issue #192.
Tested on the GE2/1 integration setup in B904.