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Add OH FPGA slow-control phase scan

Antonello Pellecchia requested to merge feature/oh-fpga-phase-scan into main


This MR adds a phase scan for the FPGA slow control e-link. For each phase from 0 to 15 the scan sends many times (by default 50 times) a signal through the e-link by writing the register BEFE.GEM.OH.OH*.FPGA.CONTROL.LOOPBACK.DATA and reads the loopback value from the same register. If the read value is different from the written one, the phase is marked as bad.

The raw and analysed results are saved in /tmp/gemdata/fpgaSlowControlPhaseScan/. The analysed result contains the optimal phase determined in the window of good phases.

Related Issue

This MR addresses issue #192.

How Has This Been Tested?

Tested on the GE2/1 integration setup in B904.

Types of changes

  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)


  • My code follows the code style of this project.
  • My change requires a change to the documentation.
  • I have updated the documentation accordingly.
  • I have read the CONTRIBUTING document.
  • I have added tests to cover my changes.
  • All new and existing tests passed.
Edited by Antonello Pellecchia

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