Description
As the title says, this MR implements a set of enhancements targeting the lpGBT v1 & ASIAGO v2 compatibility.
Most of the changes are related to the generalization and improvement of the IC communication with the GBT chips:
- Add support for the lpGBT v1 IC communication
- Select the right IC frame format and I2C address
- Allow the usage of different register ranges
- Implement the lpGBT default configuration file format
- Add checked read and checked write GBT IC accesses
- Maintain the possibility of unsafe transactions when required (i.e. enabling the VTRx+ v2.3 lasers)
- Workaround the curious case of register 248 on GE1/1
The particularities of the master-slave lpGBT topology lead to a special software blaster routine for ME0.
This set of changes should allow taking a GBT phase to ensure good VFAT communication. Also, note that the GBT phases are now set via the hardware eLink numbers rather than the logical eLink numbers for GEx/1.
Related Issue
Part of &3.
How Has This Been Tested?
Preliminary tests performed:
-
GBTx - GEx/1 (GE1/1 integration setup) -
lpGBT v1 - ASIAGO v2 - ME0 (ME0 stack setup)
More thorough tests are still required, particularly looking for regressions on GEx/1 in the last commit:
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GBTx - GEx/1 (GE1/1 integration setup) -
lpGBT v1 - ASIAGO v2 - ME0 (ME0 stack setup)
Types of changes
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Bug fix (non-breaking change which fixes an issue) -
New feature (non-breaking change which adds functionality) -
Breaking change (fix or feature that would cause existing functionality to change)
Checklist:
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My code follows the code style of this project. -
My change requires a change to the documentation. -
I have updated the documentation accordingly. -
I have read the CONTRIBUTING document. -
I have added tests to cover my changes. -
All new and existing tests passed.