LOC post-ISERDES flip-flops
A lot of the tight timing in both GE11 and GE21 OH comes from transition from the ISERDES to the set of FFs next to it.
XAPP881 recommends constraining them manually to help achieve timing closure and consistent results but I never got around to it.
I made a simple script that sets SLICE location constraints for all the FFs and it seems quite successful so far. I'm trying to double check that all placements are ok.
Relative placements are taken from the XAPP881 example where they are placed in X0Y0 and X1Y1 relative to the ISERDES.
I used absolute placements and just generated a constraints file by script because I couldn't figure out how to use RLOC for a block that contains ISERDES and SLICE elements... there is some info about using the "RPM GRID" for heterogeneous elements but it is pretty poorly documented.
INST "OVERSAMPLE_14/DR/ii_0" LOC=SLICE_X62Y28;
INST "OVERSAMPLE_14/DR/ii_2" LOC=SLICE_X62Y28;
INST "OVERSAMPLE_14/DR/ii_4" LOC=SLICE_X62Y28;
INST "OVERSAMPLE_14/DR/ii_6" LOC=SLICE_X62Y28;
INST "OVERSAMPLE_14/DR/ii_1" LOC=SLICE_X63Y28;
INST "OVERSAMPLE_14/DR/ii_3" LOC=SLICE_X63Y28;
INST "OVERSAMPLE_14/DR/ii_5" LOC=SLICE_X63Y28;
INST "OVERSAMPLE_14/DR/ii_7" LOC=SLICE_X63Y28;
I don't quite understand how in XAPP881 they constrain to max delay of 0.6 ns.. I get timing errors for less than 1.5ns
from the example ucf:
NET "*/Q<*>" MAXDELAY = 0.600 ns;
Even if some further investigation could be done to optimize the placement I think it is still strictly better than the current firmware. There's no functional change related to this besides tightening the timing constraints so I think its a pretty safe change.