Fix Makefile for single flavor projects, ease timing in DAQ, fix csc_apex top file, fix IC controller output port
- update Makefile to include flavor argument to generate_registers in all projects
- fix csc_apex top file
- fix in GBT IC controller (had been using reading output port)
- add a register stage at the output of vfat_input_serializer to ease timing. Note: an improvement on clk40 and clk80 skew could be done by using BUFGCE_DIV to divide the clocks instead of MMCM
- update regtools to print arguments it was called with