Add a 125 MHz oscillator to synthesizer B passthrough on the CTP7

The title should say it all... More specifically, these changes are an attempt to allow pure local clock operations on the CTP7.

The first commit deals with clocking scheme constraints and implements a solution to slightly relax them. The main idea is the following:

• Synthesizer A inputs are (1) the backplane TTC clock and (2) the onboard 125 MHz oscillator
• Synthesizer B inputs are (1) the backplane TTC clock and (2) a Virtex-7 FPGA output

Until now, synthesizer A was used to drive the local DAQ MGT whereas synthesizer B was used to drive the GBTx/lpGBT MGT. In local clock mode, the GBTx/lpGBT can be generated from the 125 MHz oscillator, connected directly to synthesizer A. This allows one to easily switch between the TTC and local clocks. In this scenario, the local DAQ clock can no longer be generated from synthesizer A. However, it is possible to drive synthesizer B from the Virtex-7 FPGA, which, in turn, receives a 125 MHz clock directly from the onboard oscillator. Using the passthrough in local clock mode is less adapted since the GBTx/lpGBT clock is used to drive the main TTC MMCM within the Virtex-7. Delaying the synthesizer B lock until the FPGA programming is potentially less problematic.

The second commit simplifies the firmware behavior in case a pure local clock is desired. Since the system/SLR split both in firmware and in software, this is the only clean way to deal with the situation (due to some system-level TTC registers still being exposed through the first SLR address space). This simple change removed tens of intricate lines of code in the online software.

Those minimal changes have been successfully tested on the 13 CTP7 of the P5 production system. The online software is surprisingly compatible as-is with the changes, but does not benefit (yet) from them.