CSC firmware fixes, reorganized ME0 with 8 GBTs per OH (fully tested on APEX)

FEATURE: Functional CSC firmware for CVP13 and APEX (not tested with DMBs yet)
FEATURE: gbt.py updated to reflect the new ME0 VFAT mapping, also the phase scans now use L1As and check DAQ event CRC error counts to enhance the error detection
FEATURE: reorganized ME0 with 8 GBTs and 24 VFATs per "OH"
FEATURE: option to have async axi and ipb clocks (used in CVP13 due to high AXI clk frequency)
FEATURE: configurable VFAT HDLC addresses for each slot (defaults depend on the fw flavor)
FEATURE: regtools support non-constant default values (e.g. referencing a local constant)
FEATURE: gbt phase scans reorganized, and support checking DAQ CRC errors in addition to slow control and sync errors, and sets the best phase to each elink after the scan
FEATURE: updated sca.py to use correct JTAG commands for Artix7 (only FPGA_ID tested)
FEATURE: XVC server using OH SCA JTAG -- not fully working yet (vivado sends some commands that are executed, but then it gives up and says that there are no devices on the chain)
FEATURE: updated GBTX core reset sequence, also MGT rxslide is now used instead of fabric based bitslipping for header search (solved CTP7 GBTX instabilities)
FEATURE: turned off rx sync fifos on both GBTX and LpGBT cores (they were causing instabilities)
FEATURE: SEM injection testing script added
FEATURE: increase the width of the VFAT DAQ event cnt from 8 to 16