First pass at implementing a cluster daq
I have made an attempt at a simple cluster DAQ.. It is just a controller around an XPM fifo with a bit of logic to convert from 128 bits / bx that are saved and 32 bits / transaction that are read out.
I've tested it in simulation and can see that I read out 4096 clusters in the expected consecutive order (I am just enumerating the addresses as 0-->1-->2-->3-->2047-->0)
It reads exactly 4096 clusters (512 bx) before it reports as empty.
The interface is a 32 bit word which reads out 2 clusters / transaction. The control signals are tied to fw_read_pulse_signal and fw_read_ready_signal so it should automatically retrieve the word when you read from the FIFO_DATA register and will bus error if you read from the FIFO while empty.
It shares some logic with the existing s-bit monitor so the registers are in the same place, and the reset (re-arm) is shared between them.
L1As are stuffed into the dataformat as discussed.
It can trigger either on S-bits or L1A (controlled by FIFO_EN_SBIT_TRIGGER and FIFO_EN_L1A_TRIGGER-- by default the SBIT_TRIGGER is enabled).
A delay of 1-1024 bx can be applied by the FIFO_TRIGGER_DELAY register (set 0 to 1023, there is an intrinsic +1 in the delay line).
I am attempting to compile right now but if things go well I am hoping somebody might be able to test in the future? I think @jcarlson volunteered, or maybe I volunteered him :)
Thanks!
Andrew
Closes #36 (closed)