Explore projects
-
HPTD / tclink
CERN Open Hardware Licence Version 2 - Weakly ReciprocalTiming Compensated Link
Updated -
Updated
-
Updated
-
Firmware for the PBv3 mass tester active board.
Updated -
-
GBT-SC for FPGA: This module (VHDL) allows performing slow-control of the front-end through GBT links (GBTx and SCA configuration)
Updated -
-
Updated
-
-
Updated
-
Updated
-
-
atlas-tdaq-felix / wuppercodegen
Apache License 2.0[MD, FS] JINJA based register automatic generation tool
Updated -
-
The BTrain-over-WhiteRabbit project provides a set of IP cores that implement a transport layer to be used for transmission of BTrain-related information over WR network. See project wiki
Updated -
-
Example design: implementation of the LpGBT-FPGA in a simulation testbench
Updated -
Updated
-
Updated