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FMC nanoFIP test HDL for SPEC

Firmware for PCIe cards which run with YARR sw.

Development of the MGT module for the lpGBT protocol for use in a stratix 10 FPGA (L or H tile)

SLAC Ultimate RTL Framework

IP for Caribou Peary firmware: Data FIFO with AXI interface to CPU

Module for adding timestamp information into the data stream.

HW IP core for controlling the pulser on the CaR board over an AXI bus

Firmware for Bunch Length Measurement in the CERN PS.

Firmware for PCIe cards which run with YARR sw.

Peary Caribou DAQ firmware

Old copy of https://ohwr.org/project/svec. That git repository has been rewritten to remove all PCB stuff (it is on EDMS) and to add HDL and software

RTL and verification code of the CLICpix2 chip.