@@ -56,6 +56,4 @@ The vivado folder includes two projects:
The KCU105 test bench is used to validate the routing feasibility of the LpGBT-FPGA. Especially from the timing point of view. Additionally. it used to qualify the IP by measuring the coding gain and latency.
<divstyle="border: 1px solid #faebcc; background:#fcf8e3; color:#8a6d3b; padding: .75rem 1.25rem; border-radius: .25rem;"><b>Latency mode:</b> By default, the example design runs in "standard" mode, meaning that the phase could jump by 3.125ns. To fix the Tx latency, the HPTD module can be used, giving a resolution of 1ps. The Rx latency can be fixed by using the PMA mode (see constraint file / frame aligner config) [Not recommended by Xilinx]</div>