RefClk of Kintex UltraScale
The top level HDL file lpgbtfpga_kcu105_10g24_top.vhd has the following lines:
-- Comment: * The MGT reference clock MUST be provided by an external clock generator.
-- * The MGT reference clock frequency must be 120MHz for the latency-optimized GBT Bank.
SMA_MGT_REFCLK_P : in std_logic;
SMA_MGT_REFCLK_N : in std_logic;
This is WRONG. The MGT RefClk should be around 320 MHz (to be precise 8x the LHC freq).
I recommend to correct the comment and maybe move it closer to the beginning of the file.
As additional information the datasheet ds892-kintex-ultrascale-data-sheet (May 21, 2019) , for the VMGTREFCLK GTH and GTY transceiver reference clocks absolute input voltage has : Min = –0.500 V ; Max = 1.320 V.
This implies that injecting an LVDS clock is outside the Absolute Maximum Ratings, and can permanently damage the FPGA.
Tullio