Skip to content

LPGBTFPGA (code can now be instantiated in a Verilog environment)

Pedro Vicente Leitao requested to merge lpgbtfpga_blmasic_pedro into master

The source code was updated so that it can be instantiated in a Verilog environment.

The motivation for this branch was so that the LPGBTFPGA-sim could be instantiated in a Verilog environment to facilitate ASIC designers. The following environment was used:

  • multiple BLMASIC asics (TSMC130, tapeout in 2018Q2) as the front-end device, connected to the lpgbt_model (80 Mbps e-link) (https://gitlab.cern.ch/blmasics/blmasics_rtl)

  • the lpgbt_model as the lpgbt instantiation in TRX mode (5.12Gb/s tx with FEC12) (https://gitlab.cern.ch/lpgbt/lpgbt_model)

  • the lpgbt-fpga-simulation as the lpgbt_model counter part (this repo)

  • bidirectional data transmission (further encoded in 8b10b) has been proven to work between back-end and FE asic (using the lpgbtlink)

  • the signal downlink_skipCycle was added so that skipCycles could be generated in the lpgbt. This will emulate a loss of lock (or bitslip) in the downlink path, forcing the lpgbt to search for a new header. This is one of the worst error mechanisms that can occur in a radiation environment (besides latchup!)

downlink_skipCycle : in std_logic_vector(1 downto 0); --! skipCycle in the downlink frame. makes the lpGBT lose lock and forces a new relock; this is clk'ed with txclk

Pedro.Leitao@cern.ch

Merge request reports