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Resolve "Fix deinterleaver issue (FEC5 / 10G mode)"

Merged Resolve "Fix deinterleaver issue (FEC5 / 10G mode)"
2-fix-deinterleaver-issue-fec5-10g-mode into master
Merged Julian Maxime Mendez requested to merge 2-fix-deinterleaver-issue-fec5-10g-mode into master
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dataPath/uplink_deinterleaverFec5.vhd
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@@ -14,7 +14,7 @@ use work.lpgbtfpga_package.all;
--! @brief upLinkDeinterleaver_fec5 - Uplink data de-interleaver for FEC5 configuration
--! @details De-interleaves the data to extract the encoded message from
--! the received frame. Interleaving data improves the decoding efficiency
--! the received frame. Interleaving data improves the decoding efficiency
--! by increasing the number of consecutive bits with errors that can be
--! corrected.
ENTITY upLinkDeinterleaver_fec5 IS
@@ -23,7 +23,7 @@ ENTITY upLinkDeinterleaver_fec5 IS
);
PORT (
-- Data
data_i : in std_logic_vector(255 downto 0); --! Input frame from the Rx gearbox (data shall be duplicated in upper/lower part of the frame @5.12Gbps)
data_i : in std_logic_vector(255 downto 0); --! Input frame from the Rx gearbox (data shall be duplicated in upper/lower part of the frame @5.12Gbps)
data_o : out std_logic_vector(233 downto 0); --! Output data for FEC5 encoding (data is duplicated in upper/lower part of the frame @5.12Gbps)
fec_o : out std_logic_vector(19 downto 0); --! Output FEC for FEC5 encoding (data is duplicated in upper/lower part of the frame @5.12Gbps)
@@ -40,32 +40,32 @@ END upLinkDeinterleaver_fec5;
--! * *10.24Gbps*: C0/C1/C0/C1/... Allows correcting 2 consecutive symbols
--! * *5.12Gbps*: No interleaving ... Allows correcting 1 consecutive symbols
ARCHITECTURE behavioral of upLinkDeinterleaver_fec5 IS
signal data_5g12_s : std_logic_vector(233 downto 0); --! Data output for 5.12Gbps configuration
signal fec_5g12_s : std_logic_vector(19 downto 0); --! FEC output for 5.12Gbps configuration
signal data_10g24_s : std_logic_vector(233 downto 0); --! Data output for 10.24Gbps configuration
signal fec_10g24_s : std_logic_vector(19 downto 0); --! FEC output for 10.24Gbps configuration
BEGIN --========#### Architecture Body ####========--
BEGIN --========#### Architecture Body ####========--
-- Logic
fec5_5g12: if DATARATE = DATARATE_5G12 or DATARATE = DYNAMIC generate
-- Code 0
data_5g12_s(117) <= '0';
data_5g12_s(116) <= '0';
data_5g12_s(115 downto 0) <= data_i(125 downto 10);
fec_5g12_s(9 downto 0) <= data_i(9 downto 0);
-- Code 1 (Not used @5.12Gbps - then uses 2nd phase of data)
data_5g12_s(233) <= '0';
data_5g12_s(232 downto 117) <= data_i(253 downto 138);
data_5g12_s(232 downto 117) <= data_i(253 downto 138);
fec_5g12_s(19 downto 10) <= data_i(137 downto 128);
end generate;
fec5_10g24: if DATARATE = DATARATE_10G24 or DATARATE = DYNAMIC generate
-- Code 0
data_10g24_s(233 downto 232) <= data_i(253 downto 252);
data_10g24_s(116 downto 0) <= data_i(251 downto 250) &
@@ -92,9 +92,9 @@ BEGIN --========#### Architecture Body ####========--
data_i(44 downto 40) &
data_i(34 downto 30) &
data_i(24 downto 20);
fec_10g24_s(9 downto 0) <= data_i(14 downto 10) & data_i(4 downto 0);
-- Code 1
data_10g24_s(231 downto 117) <= data_i(249 downto 245) &
data_i(239 downto 235) &
@@ -119,11 +119,11 @@ BEGIN --========#### Architecture Body ####========--
data_i(49 downto 45) &
data_i(39 downto 35) &
data_i(29 downto 25);
fec_10g24_s(19 downto 10) <= data_i(19 downto 15) & data_i(9 downto 5);
end generate;
-- Mux
data_o <= data_i(253 downto 20) when bypass = '1' and (DATARATE = DATARATE_10G24 or (DATARATE = DYNAMIC and datarate_select_i = '1')) else
data_5g12_s when bypass = '1' else
@@ -134,7 +134,7 @@ BEGIN --========#### Architecture Body ####========--
fec_5g12_s when bypass = '1' else
fec_5g12_s when DATARATE = DATARATE_5G12 or (DATARATE = DYNAMIC and datarate_select_i = '0') else
fec_10g24_s;
END behavioral;
--=================================================================================================--
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