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gbt-fpga
lpgbt-fpga
Merge requests
!6
add support for 256-bit MGT databus interface
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Closed
add support for 256-bit MGT databus interface
lruckman/lpgbt-fpga:master
into
master
Overview
0
Commits
3
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0
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2
Closed
Larry Lou Jr Ruckman
requested to merge
lruckman/lpgbt-fpga:master
into
master
5 years ago
Overview
0
Commits
3
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0
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2
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Description
32-bit and 64-bit was previously supported
No changes required
This update provides 256-bit support
128-bit is still not supported
0
0
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master
version 1
35e65c3a
5 years ago
master (base)
and
latest version
latest version
d09faf3f
3 commits,
4 years ago
version 1
35e65c3a
2 commits,
5 years ago
2 files
+
28
−
3
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uplink/lpgbtfpga_rxgearbox.vhd
+
13
−
3
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@@ -50,8 +50,14 @@ END lpgbtfpga_rxGearbox;
--! signals.
ARCHITECTURE
behavioral
OF
lpgbtfpga_rxGearbox
IS
function
ite
(
i
:
boolean
;
t
:
integer
;
e
:
integer
)
return
integer
is
begin
if
(
i
)
then
return
t
;
else
return
e
;
end
if
;
end
function
ite
;
--==================================== User Logic =====================================--
CONSTANT
c_oversampling
:
integer
:
=
c_clockRatio
/
(
c_outputWidth
/
c_inputWidth
);
constant
c_width_ratio
:
integer
:
=
ite
(
(
c_inputWidth
>
64
),
1
,
c_outputWidth
/
c_inputWidth
);
constant
c_oversampling
:
integer
:
=
ite
(
c_inputWidth
=
256
,
1
,
ite
(
c_inputWidth
=
128
,
2
,
c_clockRatio
/
c_width_ratio
));
SIGNAL
reg0
:
std_logic_vector
(((
c_inputWidth
*
c_clockRatio
)
-1
)
downto
0
);
SIGNAL
reg1
:
std_logic_vector
(((
c_inputWidth
*
c_clockRatio
)
-1
)
downto
0
);
@@ -110,8 +116,12 @@ BEGIN --========#### Architecture Body ####========--
reg1
<=
(
OTHERS
=>
'0'
);
sta_gbRdy_s0
<=
'0'
;
cnter
:
=
c_counterInitValue
;
IF
c_counterInitValue
>
c_clockRatio
THEN
cnter
:
=
0
;
ELSE
cnter
:
=
c_counterInitValue
;
END
IF
;
ELSIF
rising_edge
(
clk_inClk_i
)
THEN
clk_dataFlag_s
<=
'0'
;
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