Possible spurious early deassertion in IC FIFO empty flag?
Hello, I'm using gbt-sc at tag gbt_sc_3_1 (commit 95d494c1).
During a register read, I'm noticing a behavior that I do not fully understand, and may be the result of a bug (or an undocumented feature).
Expected behavior: When issuing a register read, the user should wait for the empty flag of the IC RX FIFO to be deasserted. That flag should signal that the read was performed on the ASIC, the register data was received back over the GBT optical link and that it will be available on the FIFO output after the user has asserted rx_rd_i (which is read_i internally to the FIFO) for 1 clock cycle (or more if the user requested multi-register reads).
Observed behavior: When I perform a read on a register inside the GBTx, the RX FIFO deasserts the empty flag before the entire message has been received. Moreover, it looks like the data output of the IC RX FIFO is always 0x03 if a read request is issued just after the flag deassertion, and that the flag is deasserted again later, as if more data was being received despite issuing a single-byte read.
Questions:
- How should the user read back the data from the RX FIFO?
- Is the first deassertion unintentional?