- Oct 05, 2020
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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- Oct 02, 2020
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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- Oct 01, 2020
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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- Sep 25, 2020
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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- Sep 07, 2020
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Eduardo Brandao De Souza Mendes authored
Name improvement for the MMCM IP See merge request HPTD/tclink!8
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Rename MMCM IP from mmcm_tclink_ultrascale_plus to mmcm_tclink_us_and_usp to indicate that it covers both UltraScale and UltraScale+
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- Aug 31, 2020
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
Update all GTH IP cores See merge request HPTD/tclink!7
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- Aug 27, 2020
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Jeroen Hegeman authored
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- Aug 26, 2020
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Eduardo Brandao De Souza Mendes authored
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- Aug 24, 2020
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
Fix metastable registers with ASYNC_REG attributes See merge request HPTD/tclink!6
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group the clock signals passed between the MGT and the clocking network: type tr_mgt_to_clk is record txoutclk : std_logic; rxoutclk : std_logic; end record; type tr_mgt_to_clk_array is array(natural range <>) of tr_mgt_to_clk; type tr_clk_to_mgt is record txusrclk : std_logic; rxusrclk : std_logic; end record; type tr_clk_to_mgt_array is array(natural range <>) of tr_clk_to_mgt; In the example design this does not make a big difference, but it does clean up the external interface a bit, leaving (apart from basic signals like clocks, etc.) only records to be exchanged with the user-level code.
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Eduardo Brandao De Souza Mendes authored
Fine tuning constraints etc See merge request HPTD/tclink!5
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location manipulation into two files: - An xdc file with just the MGT location manipulations. - A TCL file with just the message severity manipulations. The latter can then be used as a TCL hook for implementation. This solves the issues with the message severirties not being changed.
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Eduardo Brandao De Souza Mendes authored
Additional records for cleaner interface See merge request HPTD/tclink!4
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group the clock signals passed between the MGT and the clocking network: type tr_mgt_to_clk is record txoutclk : std_logic; rxoutclk : std_logic; end record; type tr_mgt_to_clk_array is array(natural range <>) of tr_mgt_to_clk; type tr_clk_to_mgt is record txusrclk : std_logic; rxusrclk : std_logic; end record; type tr_clk_to_mgt_array is array(natural range <>) of tr_clk_to_mgt; In the example design this does not make a big difference, but it does clean up the external interface a bit, leaving (apart from basic signals like clocks, etc.) only records to be exchanged with the user-level code.
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Eduardo Brandao De Souza Mendes authored
Adding .gitignore file to ignore some Xilinx- and Vivado-specific files See merge request HPTD/tclink!3
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- Aug 20, 2020
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Jeroen Hegeman authored
Adding .gitignore file to ignore some Xilinx- and Vivado-specific files and directories (as well as Emacs backup files).
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- Aug 19, 2020
- Aug 04, 2020
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Eduardo Brandao De Souza Mendes authored
Add constraints manipulations and message severity rules to allow multiple instantiations of the same transceiver IP See merge request HPTD/tclink!2
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- Aug 03, 2020
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Jeroen Hegeman authored
Added dedicated constraints manipulations and message severity rules to 'hide' the Vivado complaints due to the multiple instantiations of the transceiver IPs.
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- Jul 31, 2020
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
IP naming cleanup, and adding GTH cores equivalent to the master GTY cores. See merge request HPTD/tclink!1
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- Jul 30, 2020
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Jeroen Hegeman authored
Renamed IP cores to a) remove unnecessary vcu118 left-overs, and b) be explicit about UltraScale+ (i.e., e4) components. Added GTH equivalent cores for the master GTY cores.
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- Jul 24, 2020
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Eduardo Brandao De Souza Mendes authored
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- Jul 16, 2020