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Commit 14c4d8f4 authored by Walter Lampl's avatar Walter Lampl
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Merge branch 'SCTDCScondLoadFix' into 'master'

Fixed optional handles in SCT_DCSConditionsStatCondAlg

See merge request atlas/athena!34486
parents b8334652 39a3a865
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......@@ -21,20 +21,16 @@ StatusCode SCT_DCSConditionsStatCondAlg::initialize() {
// CondSvc
ATH_CHECK(m_condSvc.retrieve());
if (m_returnHVTemp.value()) {
// Read Cond Handle (HV)
ATH_CHECK(m_readKeyHV.initialize());
}
// Read Cond Handle (HV)
ATH_CHECK(m_readKeyHV.initialize(m_returnHVTemp.value()));
if (m_doState) {
// Read Cond Handle (state)
ATH_CHECK(m_readKeyState.initialize());
// Write Cond Handle
ATH_CHECK(m_writeKeyState.initialize());
if (m_condSvc->regHandle(this, m_writeKeyState).isFailure()) {
ATH_MSG_FATAL("unable to register WriteCondHandle " << m_writeKeyState.fullKey() << " with CondSvc");
return StatusCode::FAILURE;
}
// Read Cond Handle (state)
ATH_CHECK(m_readKeyState.initialize(m_doState));
// Write Cond Handle
ATH_CHECK(m_writeKeyState.initialize(m_doState));
if (m_doState && m_condSvc->regHandle(this, m_writeKeyState).isFailure()) {
ATH_MSG_FATAL("unable to register WriteCondHandle " << m_writeKeyState.fullKey() << " with CondSvc");
return StatusCode::FAILURE;
}
if (m_useDefaultHV.value()) {
......
......@@ -28,13 +28,6 @@ def fastElectronSequence(ConfigFlags):
viewVerify.DataObjects += [( 'xAOD::TrigEMClusterContainer' , 'StoreGateSvc+' + CaloMenuDefs.L2CaloClusters ),
( 'TrigRoiDescriptorCollection' , 'StoreGateSvc+'+RoIs )]
from AthenaCommon.AlgSequence import AlgSequence, AthSequencer
topSequence = AlgSequence()
condSeq = AthSequencer( "AthCondSeq" )
if not hasattr( condSeq, 'SCT_DCSConditionsStatCondAlg' ):
viewVerify.DataObjects += [( 'SCT_DCSStatCondData' , 'ConditionStore+SCT_DCSStatCondData' )]
topSequence.SGInputLoader.Load += [( 'SCT_DCSStatCondData' , 'ConditionStore+SCT_DCSStatCondData' )]
from IOVDbSvc.CondDB import conddb
if not conddb.folderRequested( "/PIXEL/DCS/FSMSTATUS"):
viewVerify.DataObjects += [( 'CondAttrListCollection' , 'ConditionStore+/PIXEL/DCS/FSMSTATUS' )]
......
......@@ -59,7 +59,7 @@ class MinBiasChainConfig(ChainConfigurationBase):
( 'TagInfo' , 'DetectorStore+ProcessingTags' )]
# Make sure required objects are still available at whole-event level
from AthenaCommon.AlgSequence import AlgSequence, AthSequencer
from AthenaCommon.AlgSequence import AlgSequence
topSequence = AlgSequence()
topSequence.SGInputLoader.Load += [( 'SCT_ID' , 'DetectorStore+SCT_ID' ),
( 'PixelID' , 'DetectorStore+PixelID' ),
......@@ -75,10 +75,6 @@ class MinBiasChainConfig(ChainConfigurationBase):
if not conddb.folderRequested( '/PIXEL/DCS/FSMSTATUS' ):
verifier.DataObjects += [( 'CondAttrListCollection' , 'ConditionStore+/PIXEL/DCS/FSMSTATUS' )]
topSequence.SGInputLoader.Load += [( 'CondAttrListCollection' , 'ConditionStore+/PIXEL/DCS/FSMSTATUS' )]
condSeq = AthSequencer( "AthCondSeq" )
if not hasattr( condSeq, 'SCT_DCSConditionsStatCondAlg' ):
verifier.DataObjects += [( 'SCT_DCSStatCondData' , 'ConditionStore+SCT_DCSStatCondData' )]
topSequence.SGInputLoader.Load += [( 'SCT_DCSStatCondData' , 'ConditionStore+SCT_DCSStatCondData' )]
SpList = idAlgs[:-2]
......
......@@ -143,11 +143,6 @@ def muCombAlgSequence(ConfigFlags):
if not conddb.folderRequested( '/PIXEL/DCS/FSMSTATE' ):
extraLoads += [( 'CondAttrListCollection' , 'ConditionStore+/PIXEL/DCS/FSMSTATE' )]
from AthenaCommon.AlgSequence import AthSequencer
condSeq = AthSequencer( "AthCondSeq" )
if not hasattr( condSeq, 'SCT_DCSConditionsStatCondAlg' ):
extraLoads += [( 'SCT_DCSStatCondData' , 'ConditionStore+SCT_DCSStatCondData' )]
for decision in muonChainFilter.InputDecisions:
extraLoads += [( 'xAOD::TrigCompositeContainer' , 'StoreGateSvc+'+decision )]
......
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