- Oct 22, 2020
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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Eduardo Brandao De Souza Mendes authored
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- Oct 15, 2020
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Eduardo Brandao De Souza Mendes authored
- LOCK_MODE=1 for XCVR. This is misleading in the simulation as the lpGBT was being configured in PLL mode. - -novopt in vsim is not supported in ModelSim SE 10.7, so I replaced it for something else. - instead of emul, use the name model_wrapper as suggested by SK because this is misleading w.r.t. FPGA emulator.
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- Dec 04, 2019
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
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- Nov 27, 2019
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
Resolve "Use of the LpGBT model" Closes #1 See merge request gbt-fpga/lbgbt-fpga-simulation!3
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
Resolve "Use of lpGBT-FPGA v.2.0" Closes #2 See merge request gbt-fpga/lbgbt-fpga-simulation!4
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
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Julian Maxime Mendez authored
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- Oct 16, 2018
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Julian Maxime Mendez authored
fix typo that would set the downlink_serial to UNDEFINED when errorInject generate = 0 See merge request gbt-fpga/lbgbt-fpga-simulation!2
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Pedro Vicente Leitao authored
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Julian Maxime Mendez authored
LPGBTFPGA (code can now be instantiated in a Verilog environment) See merge request gbt-fpga/lbgbt-fpga-simulation!1
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- Oct 15, 2018
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Pedro Vicente Leitao authored
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Pedro Vicente Leitao authored
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Pedro Vicente Leitao authored
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- Sep 10, 2018
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Julian Maxime Mendez authored
- Porting to the latest version of the LpGBT-FPGA IP (v.1.1.0) - Implementation of multi cycle - Cleaning of the clock tree - Fix tcl script bug
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- Aug 20, 2018
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Pedro Vicente Leitao authored
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- Aug 17, 2018
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Pedro Vicente Leitao authored
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- Aug 14, 2018
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Pedro Vicente Leitao authored
declared rxPMAInitVal_i variable as std_logic_int(7 downto 0) so lpgbtFpga_top can be instantiated in verilog
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- Jul 10, 2018
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Julian Maxime Mendez authored
- Add submodule checkout to the startup procedure
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Julian Maxime Mendez authored
- Add LpGBT model (codecs) - Add MGT emulator - Add LpGBT-FPGA top (with dynamic instantiation) - Add stimulis
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Julian Maxime Mendez authored
- Repository creation - Add README.md file - Add LpGBT-FPGA submodule
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