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Commit ee1873c8 authored by Lennart Huth's avatar Lennart Huth
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Merge branch 'bugfix' into 'master'

Bugfix of EventLoaderTimepix4 ftoa_rise and clock dll correction

See merge request corryvreckan/corryvreckan!692
parents cf10f1ad c4b590b0
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...@@ -391,7 +391,7 @@ bool EventLoaderTimepix4::decodePacket(uint64_t dataPacket) { ...@@ -391,7 +391,7 @@ bool EventLoaderTimepix4::decodePacket(uint64_t dataPacket) {
m_toa = getToA(dataPacket); m_toa = getToA(dataPacket);
m_toa = GrayToBin(m_toa); // gray to binary conversion m_toa = GrayToBin(m_toa); // gray to binary conversion
m_ftoa_rise = getFToARise(dataPacket >> 17); m_ftoa_rise = getFToARise(dataPacket);
m_ftoa_fall = getFToAFall(dataPacket); m_ftoa_fall = getFToAFall(dataPacket);
m_tot = getToT(dataPacket); m_tot = getToT(dataPacket);
m_pileup = getPileUp(dataPacket); m_pileup = getPileUp(dataPacket);
...@@ -406,7 +406,7 @@ bool EventLoaderTimepix4::decodePacket(uint64_t dataPacket) { ...@@ -406,7 +406,7 @@ bool EventLoaderTimepix4::decodePacket(uint64_t dataPacket) {
m_uftoa_start, m_uftoa_start,
m_uftoa_stop, m_uftoa_stop,
m_tot); // full corrected ToT | units of ~195 ps (1/(640*8 MHz)) m_tot); // full corrected ToT | units of ~195 ps (1/(640*8 MHz))
m_fullToa = fullToa(m_ext_toa, m_uftoa_start, m_uftoa_stop, m_ftoa_rise) - m_fullToa = fullToa(m_ext_toa, m_uftoa_start, m_uftoa_stop, m_ftoa_rise) +
toa_clkdll_correction(m_sPGroup); // rfull corrected ToA | units of ~195 ps (1/(640*8 MHz)) toa_clkdll_correction(m_sPGroup); // rfull corrected ToA | units of ~195 ps (1/(640*8 MHz))
m_colrow = decodeColRow(m_pixel, m_sPixel, m_sPGroup, header, top); // decodes the row and col value from the address m_colrow = decodeColRow(m_pixel, m_sPixel, m_sPGroup, header, top); // decodes the row and col value from the address
......
...@@ -191,11 +191,8 @@ namespace corryvreckan { ...@@ -191,11 +191,8 @@ namespace corryvreckan {
return ((toa << 7) - (ftoa_rise << 3) + (uftoa_start - uftoa_stop)); return ((toa << 7) - (ftoa_rise << 3) + (uftoa_start - uftoa_stop));
} }
// Corrects latency delay due to DDLL clock distribution. Units are period of 40MHz (25ns) // Corrects latency delay due to DDLL clock distribution. Units are period of 8*640MHz (195 ps)
uint64_t toa_clkdll_correction(uint64_t spgroup_addr = 0) { uint64_t toa_clkdll_correction(uint64_t spgroup_addr = 0) { return spgroup_addr << 2; }
uint64_t clk_dll_step = 1 >> 5;
return (15 - spgroup_addr) * clk_dll_step;
}
// address including pixel, super pixel and super pixel group values // address including pixel, super pixel and super pixel group values
uint64_t getAddr(uint64_t packet) { return (packet >> 46) & 0x3ffff; } uint64_t getAddr(uint64_t packet) { return (packet >> 46) & 0x3ffff; }
......
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