VP sensor and ASIC dimensions and positions
Update the VP sensors and ASICs to the final designs contained in the following EDMS documents:
- https://edms.cern.ch/document/1706379/3
- https://edms.cern.ch/document/1706381/1
- https://edms.cern.ch/document/2086903/1
- https://edms.cern.ch/document/1851416/2
- https://edms.cern.ch/document/2266981/1
Fix a mismatch in the numbering of the LVs and PVs of the ladders when being placed in the module volume.
Match the nomenclature for each ladder in the comments to the nomenclature public note (one of the docs above).
Modify thickness of glue layer between substrate and chips ( 30 -> 70 microns ).
Add 20 micron layer between sensor and each chip to account for bump bonds