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Laurent Petre
0xbefe-online-ci
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debug-vfat3-sc-timeout
fe3ed4a1
·
More debugging...
·
May 03, 2024
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me0-raw-sbit-test
07c75b98
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me0: fix the raw S-bit testing feature generate condition
·
Apr 26, 2024
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gem-evb-fifo-cnt-fixes
17dfe11d
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gem/daq: fix the FIFO data count widths
·
Apr 25, 2024
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oh-relax-iserdes-timing
48abd2b4
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oh: remove set_max_delay constraints between ISERDES and DRU
·
Apr 25, 2024
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oh-sem-bugfix
9c486d6f
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oh: simplify & document the SEM registers interface
·
Apr 25, 2024
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Stale branches
feature/no-implicit-verilog-wires
a872551e
·
Disable wire implicit declaration in Verilog
·
Mar 30, 2022
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bugfix/gemloader
2d724832
·
Add the GEM loader registers into the CTP7 address table
·
Apr 29, 2022
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bugfix/axi-bridge-cdc
57c0adbe
·
Fix AXI-IPBus bridge CDC
·
Jun 03, 2022
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feature/vfat-automask
6953e7e5
·
fixup! An an option to Sync VFAT3 on TTC ReSync B-Go
·
Oct 26, 2022
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build/online-software-ci
523ac433
·
lpgbt: enable the bi-dir EC channel to the sub lpGBT
·
Oct 27, 2022
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