Initial V3.3 issue.

circuit_board/wrs_v3/miniBackplane_18Ports_SFP_V3_3/Connector_GTX.Harness

+WR_LINK_GTX=WR_LINK_RD_OUT_P,WR_LINK_RD_OUT_N,WR_LINK_TD_IN_P,WR_LINK_TD_IN_N

circuit_board/wrs_v3/miniBackplane_18Ports_SFP_V3_3/Design Rule Check - miniBackplane.drc

+Protel Design System Design Rule Check
+PCB File : D:\White Rabbit\miniBackplane_SFP\miniBackplane.PcbDoc
+Date     : 10/05/2012
+Time     : 13:11:13
+
+Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
+Rule Violations :0
+
+Processing Rule : Un-Routed Net Constraint ( (All) )
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Pad C44-1 (3.83,22.374mm) And Pad C46-1 (34.73,24.574mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Pad C50-1 (201.43,46.174mm) And Track on layer Top Layer (276.23,46.174mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Pad C52-1 (280.63,46.074mm) And Track on layer Top Layer (355.405,46.174mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Pad C49-1 (121.83,46.174mm) And Pad Free- (197.055,46.174mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Pad C53-1 (359.53,46.374mm) And Track on layer Top Layer (434.58,46.174mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Track on layer Top Layer (434.58,126.474mm) And Pad C54-1 (434.73,50.974mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Pad C50-1 (201.43,46.174mm) And Pad C43-1 (233.93,89.774mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Track on layer Top Layer (158.574,90.574mm) And Pad C43-1 (233.93,89.774mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Pad C52-1 (280.63,46.074mm) And Pad C45-1 (317.03,86.574mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Track on layer Top Layer (38.88,24.674mm) And Track on layer Top Layer (38.88,105.974mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Track on layer Top Layer (237.85,90.6mm) And Track on layer Top Layer (249.28,165.32mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Pad C47-1 (8.43,169.174mm) And Pad C41-1 (34.73,106.474mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Track on layer Top Layer (126.48,160.474mm) And Pad C42-1 (154.23,90.574mm)
+   Violation between Un-Routed Net Constraint: Net CHASSIS Between Track on layer Top Layer (38.88,24.674mm) And Track on layer Top Layer (117.88,46.174mm)
+Rule Violations :14
+
+Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
+Rule Violations :0
+
+Processing Rule : Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.5mm) (InNetClass('PWRs&GNDs'))
+Rule Violations :0
+
+Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0.254mm, Vertical Gap = 0.254mm ) (All),(All) 
+Rule Violations :0
+
+Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
+Rule Violations :0
+
+Processing Rule : Pads and Vias to follow the Drill pairs settings
+Rule Violations :0
+
+Processing Rule : Hole Size Constraint (Min=0.2mm) (Max=7mm) (All)
+Rule Violations :0
+
+Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.2mm) (Max=0.2mm) (Preferred=0.2mm) (All)
+   Violation between Differential Pairs Routing Between Net USB_DDP_P And Net USB_DDP_N
+   Violation between Differential Pairs Routing Between Net MGTTX115_2_P And Net MGTTX115_2_N
+   Violation between Differential Pairs Routing Between Net MGTTX112_0_P And Net MGTTX112_0_N
+Rule Violations :3
+
+Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Silkscreen Over Component Pads (Clearance=0.08mm) (All),(All)
+   Violation between Track (222.155mm,162.66mm)(237.485mm,162.66mm)  Top Overlay and 
+                     Pad J7-3(229.81mm,163.98mm)  Multi-Layer
+   Violation between Track (222.155mm,162.66mm)(237.485mm,162.66mm)  Top Overlay and 
+                     Pad J7-2(232.35mm,161.44mm)  Multi-Layer
+   Violation between Track (222.155mm,162.66mm)(237.485mm,162.66mm)  Top Overlay and 
+                     Pad J7-1(227.27mm,161.44mm)  Multi-Layer
+Rule Violations :3
+
+Processing Rule : Silk to Silk (Clearance=0.025mm) (All),(All)
+   Violation between Text "SE" (189.737mm,90.238mm)  Top Overlay and 
+                     Track (194.755mm,94.554mm)(197.089mm,90.219mm)  Top Overlay
+Rule Violations :1
+
+Processing Rule : Net Antennae (Tolerance=0mm) (All)
+Rule Violations :0
+
+Processing Rule : Width Constraint (Min=0.2mm) (Max=0.2mm) (Preferred=0.2mm) ((InDifferentialPairClass('All Differential Pairs')))
+Rule Violations :0
+
+Processing Rule : Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.2mm) (All)
+Rule Violations :0
+
+
+Violations Detected : 21
+Time Elapsed        : 00:00:37
\ No newline at end of file

circuit_board/wrs_v3/miniBackplane_18Ports_SFP_V3_3/SFP.Harness

+SFP_Control=SFP_TX_DISABLE,SFP_LOS,SFP_DETECT,SFP_SCL,SFP_SDA,SFP_TX_FAULT
+SFP_GTX=SFP_TD_IN_N,SFP_TD_IN_P,SFP_RD_OUT_N,SFP_RD_OUT_P

circuit_board/wrs_v3/miniBackplane_18Ports_SFP_V3_3/WR_LINK.Harness

+WR_LINK_GTX=WR_LINK_TD_IN_N,WR_LINK_TD_IN_P,WR_LINK_RD_OUT_N,WR_LINK_RD_OUT_P

circuit_board/wrs_v3/miniBackplane_18Ports_SFP_V3_3/miniBackplane_SFP.PrjPCBStructure

+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_Connector_GTX|SchDesignator=U_Connector_GTX|FileName=Connector_GTX.SchDoc|SymbolType=Normal|RawFileName=Connector_GTX.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_Connectors_GPIOs|SchDesignator=U_Connectors_GPIOs|FileName=Connectors_GPIOs.SchDoc|SymbolType=Normal|RawFileName=Connectors_GPIOs.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_I2C_Multiplexers|SchDesignator=U_I2C_Multiplexers|FileName=I2C_Multiplexers.SchDoc|SymbolType=Normal|RawFileName=I2C_Multiplexers.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_Power_Supply|SchDesignator=U_Power_Supply|FileName=Power_Supply.SchDoc|SymbolType=Normal|RawFileName=Power_Supply.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_TEST_USB|SchDesignator=U_TEST_USB|FileName=TEST_USB.SchDoc|SymbolType=Normal|RawFileName=TEST_USB.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_WR_LINK|SchDesignator=U_WR_LINK|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_WR_LINK|SchDesignator=U_WR_LINK|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_WR_LINK|SchDesignator=U_WR_LINK|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_WR_LINK|SchDesignator=U_WR_LINK|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_WR_LINK|SchDesignator=U_WR_LINK|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_WR_LINK|SchDesignator=U_WR_LINK|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_WR_LINK|SchDesignator=U_WR_LINK|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_WR_LINK|SchDesignator=U_WR_LINK|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=U_WR_LINK|SchDesignator=U_WR_LINK|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=TopLevelDocument|FileName=Main.SchDoc