Tags give the ability to mark specific points in history as being important
-
v6-17
99b06c7f · ·Tag specific for IT - Update with respect tag v6-15: Added code to check refCode If IrefCode specified value in the XML file is different from the one read out from the chip, there will be an error message If IrefCode = -1, there will NOT be any check -
v6-16
61ffa2f5 · ·Tag specific for OT Main updates since tag v6-14: - Added calibration files from wafer-level testing for MPA - Added LpGBT v2 calibration data Compatible with FW tag v3-03: https://udtc-ot-firmware.web.cern.ch/?dir=v3-03
-
v6-15
8353502b · ·Tag specific for IT - Update with respect tag v6-12: - Added grading for VTRx+ scan - Added grading for Eye Opening Monitor (EOM) - Added default behaviour for CDCE clock frequency - Added Inj. cap configurable from XML file - Correct errors for SCurve and Gain 3D Histograms
-
v6-14
5f721f6b · ·Tag specific for OT Main updates since tag v6-13: - fixed issues when filling trimming plots while running in OTSDAQ configuration Compatible with FW tag v3-03: https://udtc-ot-firmware.web.cern.ch/?dir=v3-03
-
v6-13
4c044187 · ·Tag specific for OT Main updates since tag v6-11: - improved PS trimming to reduce number of outliers - corrected issue in storing the git tag in the root file - sending end of transmission message in VTRxLightOff - calculating pedestal used for occupancy test during SCurve for 2S and trimming for PS - manually lowered the SSA threshold from 5 to 4 sigma due to occupancy too low - avoiding unwanted configuration of the CDCE - preventing ECV from getting stuck Compatible with FW tag v3-03: https://udtc-ot-firmware.web.cern.ch/?dir=v3-03
-
v6-12
f990796e · ·Tag specific for IT Update with respect tag v6-06: - Improved speed by 25% of Threshold Adjustment - Added support for AutoRead feature of the RD53 chip - Users can now use the AutoRead feature of the RD53 chip - CDCE reprogramming is now under control: - check if it was already programmed - check if the user really needs to re-program it - use of a secondary clock generator
-
v6-11
7d7f6ca8 · ·Tag specific for OT Main updates since tag v6-10: - Reduced memory usage of CIC2 event decoding - Fixed issues in storing GIT tag and commit when running with GIPHT and OTSDAQ Compatible with FW tag v3-03: https://udtc-ot-firmware.web.cern.ch/?dir=v3-03
-
v6-10
f8169319 · ·Tag specific for OT Main updates since tag v6-09: - Added BX0 alignment in the sequence - Stub package delay independent between hybrids - Correctly storing GIT tag and commit in metadata Compatible with FW tag v3-03: https://udtc-ot-firmware.web.cern.ch/?dir=v3-03
-
v6-09
d64f784d · ·Tag specific for OT: Main updates since tag v6-08 - Avoided L1 integrity test to get stuck - When an exception occurs is catched and the root file is saved before quitting - Rewriting best bitslip to ensure running stability - Using previous temperature measurement to calculate current for resistance measurement Compatible with FW tag v3-02: https://udtc-ot-firmware.web.cern.ch/?dir=v3-02
-
v6-08
6cb923f9 · ·Tag specific for OT Main updates since tag v6-07 - Bug fix on injection test for PS 5G - Minor improvements to run stability - Minor change in CM noise histogram name Compatible with FW tag v3-02: https://udtc-ot-firmware.web.cern.ch/?dir=v3-02
-
v6-07
18ec507b · ·Tag specific for OT Main updates since tag v6-02 - Included Bit error rate test from LpGBT to FC7 - Included pattern checker for stub lines in the FW to speed up - Improvements in the L1 pattern checker to read fewer packets while keeping the same amount of tested bits - Improvements in the CM noise measurement for PS and 2S - Various improvements in histograms Compatible with FW tag v3-02: https://udtc-ot-firmware.web.cern.ch/?dir=v3-02
-
v6-06
3ff505e1 · ·Tag specific for IT Update with respect tag v6-04: - Improved ThresholdAdjustment: remove periodic resets --> runs faster and it's more robust - Improved initialization sequence of CROC thanks to Fabio Luongo, see RD53BInterface (in InitRD53Uplinks swapped order Aurora config and ChannelBonding config) - Improved concurrent access to hardware (FC7) by different processes (now Monitoring should be more stable, without readout errors) - Faster ThresholdAdjustment algorithm thanks to Javier Sanchez
-
v6-05
c16cfb60 · ·Tag specific for IT - Update with respect tag v6-04: - Avoid repetition RxGroup in cfg and add the possibility to configure uplink driver strength and pre-emphasis during UpLink initialization - Fixed a small bug in percentage running time when using multiple boards - Fixed bug in compilation for EUDAQ mode - Fixed bug in voltagetuning - Fixed bug in BER-test option chain2test=2 - Removed pPrmptCfg from Chip and fixed bug in LpGBT Compatible with IT FW tag 5.0
-
v6-04
5b4c72e6 · ·Tag specific for IT difference with respect to v6-03: - Now also group number 0 (zero) is a valid number in RxGroups - Therefore non-assigned lanes are marked with N --> See documentation for more details - Added split by Board and Hybrid
-
v6-03
b3065f5b · ·Tag specific for IT - Implemented VTRx scan bias vs modulation - Implemented LpGBT eye diagram - Implemented readout of NTCs through LpGBT ADC (e.g. the NTC next to the VTRx) - No more FIFO readout errors when switching on Monitoring (many thanks to Fabio Luongo) - Fixed a small bug in the readout chip “enable” flag of XML file - Moved NTC parameters “beta” and “R@25C” to XML configuration file as requested by Sophie Rohletter in this presentation: https://indico.cern.ch/event/1485283/contributions/6260866/attachments/2981224/5249153/Temperature Readout NTC.pdf - Refined threshold adjustment (thradj) scan: long-standing issue with the stability of this scan because it unavoidably probes high-noise regions --> with the consequence of compromising the chip stability (sometimes we lose the AURORA communication) --> now, while exploring the high-noise region, we perform periodic reset/reconfiguration - MonitorData saved in the Results directory with run number --> requested by Thierry -Working with FW version 5.0
-
v6-02
ad35d9fd · ·First tag including support for PS fast counter readouts. Various speed up implemented compatible with FW version 3-01: https://udtc-ot-firmware.web.cern.ch/?dir=v3-01
-
v6-01
c021f33f · ·Added LpGBT eye scan for downlink and improved VTRx+ output light yield scan Compatible with FW tag v3-00
-
v6-00
72ad9a24 · ·Preliminary tag for OT module pre-production Added fullTest and quickTest for PS and 2S modules Compatible with FW tag v3-00
-
v5-04
8b212c97 · ·IT updates: - Added check on e-fuse code for every chip (CROC) --> added field eFuseCode in XML file - Fixed bug in CROC initialisation sequence (no need to run DataIntegrity twice at power up) OT updates: - Electric Chain Validation completed for both PS and 2S
-
v5-03
e67c83da · ·Updates for IT: - New thradj algorithm: the golden-ratio algorithm runs on one chip at a time per module (all modules in parallel) - DoDataIntegrity now also works for RD53A - DoDataIntegrity now also with option 3 masks at Core level - LpGBT I2C-slave chips handled as if they were LpGBT registers - Silent Running in thradj and RD53Interface