Newer
Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Wed Apr 17 13:56:09 2019
# Process ID: 20636
# Current directory: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01
# Command line: vivado DAQ_socket_loopback_01.xpr
# Log file: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/vivado.log
# Journal file: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/vivado.jou
#-----------------------------------------------------------
start_gui
open_project DAQ_socket_loopback_01.xpr
CRITICAL WARNING: [Project 1-19] Could not find the file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/IBUFDS.v'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/DSinput.v'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/PatterunFilter.v'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/SeriPara.v'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/ip_repo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/onishi/Xilinx/Vivado/2017.4/data/ip'.
update_compile_order -fileset sources_1
export_ip_user_files -of_objects [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/DSinput.v] -no_script -reset -force -quiet
remove_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/DSinput.v
export_ip_user_files -of_objects [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/IBUFDS.v] -no_script -reset -force -quiet
remove_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/IBUFDS.v
export_ip_user_files -of_objects [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/PatterunFilter.v] -no_script -reset -force -quiet
remove_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/PatterunFilter.v
export_ip_user_files -of_objects [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/SeriPara.v] -no_script -reset -force -quiet
remove_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/SeriPara.v
add_files -norecurse {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/new/IBUFDS.v /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/new/PatterunFilter.v /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/new/DSinput.v /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/new/SeriPara.v}
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_processing_system7_0_0
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_100M
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_rst_ps7_0_100M_0
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_ps7_0_axi_periph_0
Adding cell -- xilinx.com:ip:selectio_wiz:5.1 - selectio_wiz_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_selectio_wiz_0_0
INFO: [Device 21-403] Loading part xc7z020clg484-1
The HP banks in device are && local var set to 0 && devicetype is 3
The HP banks in device are && local var set to 0 && devicetype is 3
The HP banks in device are && local var set to 0 && devicetype is 3
Adding cell -- xilinx.com:ip:clk_wiz:5.4 - clk_wiz_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_clk_wiz_0_0
Adding cell -- xilinx.com:ip:selectio_wiz:5.1 - selectio_wiz_1
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_selectio_wiz_1_0
The HP banks in device are && local var set to 0 && devicetype is 3
The HP banks in device are && local var set to 0 && devicetype is 3
The HP banks in device are && local var set to 0 && devicetype is 3
Adding cell -- xilinx.com:ip:system_ila:1.1 - system_ila_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_system_ila_0_0
Adding cell -- xilinx.com:module_ref:SeriPara:1.0 - SeriPara_0
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/ip_repo'.
INFO: [BD 41-1728] Could not find a module with name: design_1_SeriPara_0_0
Adding cell -- user.org:user:patternFilter_cfg:1.0 - patternFilter_cfg_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_patternFilter_cfg_0_0
Adding cell -- xilinx.com:module_ref:PatterunFilter:1.0 - PatterunFilter_0
INFO: [BD 41-1728] Could not find a module with name: design_1_PatterunFilter_0_0
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_wiz_0/clk_out2(clk) and /SeriPara_0/clk_in(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_wiz_0/clk_out2(clk) and /PatterunFilter_0/clk_in(undef)
Adding cell -- user.org:user:AXIStream_Converter:1.0 - AXIStream_Converter_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_AXIStream_Converter_0_0
Adding cell -- user.org:user:AXIS_Converter_cfg:1.0 - AXIS_Converter_cfg_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_AXIS_Converter_cfg_0_0
Adding cell -- xilinx.com:ip:axi_dma:7.1 - axi_dma_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_axi_dma_0_0
Adding cell -- user.org:user:DMAamount:1.0 - DMAamount_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_DMAamount_0_0
Adding cell -- user.org:user:FIFO_STATUS:1.0 - FIFO_STATUS_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_FIFO_STATUS_0_0
Adding cell -- xilinx.com:ip:fifo_generator:13.2 - fifo_generator_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_fifo_generator_0_0
INFO: [xilinx.com:ip:fifo_generator:13.2-5968] /DAQ/fifo_generator_0Executing the post_config_ip from bd
Adding cell -- user.org:user:busy_controller:1.0 - busy_controller_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_busy_controller_0_0
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_axi_mem_intercon_0
Adding cell -- xilinx.com:ip:fifo_generator:13.2 - fifo_generator_1
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_fifo_generator_1_0
INFO: [xilinx.com:ip:fifo_generator:13.2-5968] /DAQ/fifo_generator_1Executing the post_config_ip from bd
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_auto_pc_1
Adding cell -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_auto_us_0
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
INFO: [BD 41-434] Could not find an IP with XCI file by name: design_1_xbar_0
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Successfully read diagram <design_1> from BD file </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd>
INFO: [BD 41-433]
Design successfully migrated to use XCI files...
open_bd_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:55 . Memory (MB): peak = 6803.148 ; gain = 454.836 ; free physical = 1036 ; free virtual = 18562
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
regenerate_bd_layout
The HP banks in device are && local var set to 0 && devicetype is 3
The HP banks in device are && local var set to 0 && devicetype is 3
The HP banks in device are && local var set to 0 && devicetype is 3
The HP banks in device are && local var set to 0 && devicetype is 3
The HP banks in device are && local var set to 0 && devicetype is 3
The HP banks in device are && local var set to 0 && devicetype is 3
startgroup
set_property -dict [list CONFIG.CLKOUT3_USED {true} CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {200.000} CONFIG.MMCM_DIVCLK_DIVIDE {1} CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} CONFIG.MMCM_CLKOUT0_DIVIDE_F {20.000} CONFIG.MMCM_CLKOUT1_DIVIDE {5} CONFIG.MMCM_CLKOUT2_DIVIDE {4} CONFIG.NUM_OUT_CLKS {3} CONFIG.CLKOUT1_JITTER {174.629} CONFIG.CLKOUT1_PHASE_ERROR {114.212} CONFIG.CLKOUT2_JITTER {131.841} CONFIG.CLKOUT2_PHASE_ERROR {114.212} CONFIG.CLKOUT3_JITTER {126.455} CONFIG.CLKOUT3_PHASE_ERROR {114.212}] [get_bd_cells clk_wiz_0]
endgroup
startgroup
set_property -dict [list CONFIG.CLKOUT3_USED {false} CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200.000} CONFIG.MMCM_DIVCLK_DIVIDE {1} CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} CONFIG.MMCM_CLKOUT0_DIVIDE_F {25.000} CONFIG.MMCM_CLKOUT1_DIVIDE {5} CONFIG.MMCM_CLKOUT2_DIVIDE {1} CONFIG.NUM_OUT_CLKS {2} CONFIG.CLKOUT1_JITTER {159.371} CONFIG.CLKOUT1_PHASE_ERROR {98.575} CONFIG.CLKOUT2_JITTER {114.829} CONFIG.CLKOUT2_PHASE_ERROR {98.575}] [get_bd_cells clk_wiz_0]
endgroup
regenerate_bd_layout
startgroup
endgroup
validate_bd_design
WARNING: [BD 41-1781] Updates have been made to one or more nets/interface connections marked for debug.
Debug nets, which are already connected to System ILA IP core in the block-design, will be automatically available for debug in Hardware Manager.
For unconnected Debug nets, please open synthesized design and use 'Set Up Debug' wizard to insert, modify or delete Debug Cores. Failure to do so could result in critical warnings and errors in the implementation flow.
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wstrb has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_wready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wdata has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wlast has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bresp has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awburst has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awaddr has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_awready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_bready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awsize has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awcache has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awprot has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awlen has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/DAQ/FIFO_STATUS_0/fifo_wr_data_count
/DAQ/FIFO_STATUS_0/fifo_rd_data_count
validate_bd_design -force
WARNING: [BD 41-1781] Updates have been made to one or more nets/interface connections marked for debug.
Debug nets, which are already connected to System ILA IP core in the block-design, will be automatically available for debug in Hardware Manager.
For unconnected Debug nets, please open synthesized design and use 'Set Up Debug' wizard to insert, modify or delete Debug Cores. Failure to do so could result in critical warnings and errors in the implementation flow.
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wstrb has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_wready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wdata has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wlast has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bresp has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awburst has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awaddr has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_awready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_bready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awsize has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awcache has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awprot has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awlen has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/DAQ/FIFO_STATUS_0/fifo_wr_data_count
/DAQ/FIFO_STATUS_0/fifo_rd_data_count
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
make_wrapper -files [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd] -top
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wstrb has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_wready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wdata has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wlast has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bresp has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awburst has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awaddr has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_awready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_bready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awsize has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awcache has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awprot has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awlen has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/DAQ/FIFO_STATUS_0/fifo_wr_data_count
/DAQ/FIFO_STATUS_0/fifo_rd_data_count
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/synth/design_1.v
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/sim/design_1.v
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
add_files -norecurse /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
update_compile_order -fileset sources_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
[Wed Apr 17 14:16:49 2019] Launched synth_1...
Run output will be captured here: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/synth_1/runme.log
[Wed Apr 17 14:16:49 2019] Launched impl_1...
Run output will be captured here: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/runme.log
create_bd_cell -type module -reference DSinput DSinput_0
delete_bd_objs [get_bd_cells DSinput_0]
export_ip_user_files -of_objects [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/new/DSinput.v] -no_script -reset -force -quiet
remove_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/new/DSinput.v
update_module_reference design_1_DSinput_0_0
ERROR: [filemgmt 56-189] Failed to resolve reference. Nothing was found in the project to match the name 'DSinput'.
ERROR: [Common 17-39] 'update_module_reference' failed due to earlier errors.
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
validate_bd_design
WARNING: [BD 41-1781] Updates have been made to one or more nets/interface connections marked for debug.
Debug nets, which are already connected to System ILA IP core in the block-design, will be automatically available for debug in Hardware Manager.
For unconnected Debug nets, please open synthesized design and use 'Set Up Debug' wizard to insert, modify or delete Debug Cores. Failure to do so could result in critical warnings and errors in the implementation flow.
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wstrb has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_wready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wdata has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wlast has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bresp has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awburst has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awaddr has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_awready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_bready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awsize has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awcache has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awprot has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awlen has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/DAQ/FIFO_STATUS_0/fifo_wr_data_count
/DAQ/FIFO_STATUS_0/fifo_rd_data_count
export_ip_user_files -of_objects [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/new/IBUFDS.v] -no_script -reset -force -quiet
remove_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/new/IBUFDS.v
make_wrapper -files [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd] -top
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wstrb has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_wready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wdata has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wlast has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bresp has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awburst has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awaddr has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_awready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_bready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awsize has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awcache has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awprot has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awlen has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/DAQ/FIFO_STATUS_0/fifo_wr_data_count
/DAQ/FIFO_STATUS_0/fifo_rd_data_count
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/synth/design_1.v
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/sim/design_1.v
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/ip_repo'.
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wstrb has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_wready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wdata has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wlast has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bresp has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awburst has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awaddr has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_awready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_bready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awsize has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awcache has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awprot has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awlen has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/DAQ/FIFO_STATUS_0/fifo_wr_data_count
/DAQ/FIFO_STATUS_0/fifo_rd_data_count
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/synth/design_1.v
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/sim/design_1.v
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_100M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block selectio_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block selectio_wiz_1 .
Exporting to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0_1/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
Generated Block Design Tcl file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0_1/bd_0/hw_handoff/design_1_system_ila_0_0_bd.tcl
Generated Hardware Definition File /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0_1/bd_0/synth/design_1_system_ila_0_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block SeriPara_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block patternFilter_cfg_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block PatterunFilter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/AXIStream_Converter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/AXIS_Converter_cfg_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/axi_dma_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/DMAamount_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/FIFO_STATUS_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/busy_controller_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/fifo_generator_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_1_1/design_1_auto_pc_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/axi_mem_intercon/s00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0_1/design_1_auto_us_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/axi_mem_intercon/s00_couplers/auto_us .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0_1/design_1_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
Generated Block Design Tcl file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
Generated Hardware Definition File /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/synth/design_1.hwdef
[Wed Apr 17 14:27:21 2019] Launched design_1_selectio_wiz_0_0_synth_1, design_1_rst_ps7_0_100M_0_synth_1, design_1_DMAamount_0_0_synth_1, design_1_AXIS_Converter_cfg_0_0_synth_1, design_1_axi_dma_0_0_synth_1, design_1_FIFO_STATUS_0_0_synth_1, design_1_processing_system7_0_0_synth_1, design_1_AXIStream_Converter_0_0_synth_1, design_1_selectio_wiz_1_0_synth_1, design_1_PatterunFilter_0_0_synth_1, design_1_patternFilter_cfg_0_0_synth_1, design_1_SeriPara_0_0_synth_1, design_1_clk_wiz_0_0_synth_1, design_1_fifo_generator_0_0_synth_1, design_1_xbar_0_synth_1, design_1_system_ila_0_0_synth_1, design_1_busy_controller_0_0_synth_1, design_1_fifo_generator_1_0_synth_1, design_1_auto_pc_0_synth_1, design_1_auto_us_0_synth_1, design_1_auto_pc_1_synth_1, synth_1...
Run output will be captured here:
design_1_selectio_wiz_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_selectio_wiz_0_0_synth_1/runme.log
design_1_rst_ps7_0_100M_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_rst_ps7_0_100M_0_synth_1/runme.log
design_1_DMAamount_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_DMAamount_0_0_synth_1/runme.log
design_1_AXIS_Converter_cfg_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_AXIS_Converter_cfg_0_0_synth_1/runme.log
design_1_axi_dma_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_axi_dma_0_0_synth_1/runme.log
design_1_FIFO_STATUS_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_FIFO_STATUS_0_0_synth_1/runme.log
design_1_processing_system7_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_processing_system7_0_0_synth_1/runme.log
design_1_AXIStream_Converter_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_AXIStream_Converter_0_0_synth_1/runme.log
design_1_selectio_wiz_1_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_selectio_wiz_1_0_synth_1/runme.log
design_1_PatterunFilter_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_PatterunFilter_0_0_synth_1/runme.log
design_1_patternFilter_cfg_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_patternFilter_cfg_0_0_synth_1/runme.log
design_1_SeriPara_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_SeriPara_0_0_synth_1/runme.log
design_1_clk_wiz_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_clk_wiz_0_0_synth_1/runme.log
design_1_fifo_generator_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_fifo_generator_0_0_synth_1/runme.log
design_1_xbar_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_xbar_0_synth_1/runme.log
design_1_system_ila_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_system_ila_0_0_synth_1/runme.log
design_1_busy_controller_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_busy_controller_0_0_synth_1/runme.log
design_1_fifo_generator_1_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_fifo_generator_1_0_synth_1/runme.log
design_1_auto_pc_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_auto_pc_0_synth_1/runme.log
design_1_auto_us_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_auto_us_0_synth_1/runme.log
design_1_auto_pc_1_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_auto_pc_1_synth_1/runme.log
synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/synth_1/runme.log
[Wed Apr 17 14:27:23 2019] Launched impl_1...
Run output will be captured here: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:30 ; elapsed = 00:00:27 . Memory (MB): peak = 7388.133 ; gain = 151.391 ; free physical = 347 ; free virtual = 17980
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
add_files -fileset constrs_1 -norecurse /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/constrs_1/new/DAQ_byDMA_FEI4.xdc
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
[Wed Apr 17 14:44:11 2019] Launched synth_1...
Run output will be captured here: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/synth_1/runme.log
[Wed Apr 17 14:44:11 2019] Launched impl_1...
Run output will be captured here: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/runme.log
file mkdir /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk
file copy -force /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/design_1_wrapper.sysdef /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
launch_sdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
INFO: [Vivado 12-4158] Exported Hardware file is out of date. Exported hardware information may be inconsistent with respect to the current state of the design. It is recommended that you re-export the design and launch SDK otherwise SDK is launched with out of date hardware system file.
launch_sdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
file mkdir /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk
file copy -force /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/design_1_wrapper.sysdef /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
launch_sdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
startgroup
set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {400.000} CONFIG.MMCM_DIVCLK_DIVIDE {1} CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} CONFIG.MMCM_CLKOUT0_DIVIDE_F {20.000} CONFIG.MMCM_CLKOUT1_DIVIDE {2} CONFIG.CLKOUT1_JITTER {174.629} CONFIG.CLKOUT1_PHASE_ERROR {114.212} CONFIG.CLKOUT2_JITTER {111.164} CONFIG.CLKOUT2_PHASE_ERROR {114.212}] [get_bd_cells clk_wiz_0]
endgroup
validate_bd_design
WARNING: [BD 41-1781] Updates have been made to one or more nets/interface connections marked for debug.
Debug nets, which are already connected to System ILA IP core in the block-design, will be automatically available for debug in Hardware Manager.
For unconnected Debug nets, please open synthesized design and use 'Set Up Debug' wizard to insert, modify or delete Debug Cores. Failure to do so could result in critical warnings and errors in the implementation flow.
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wstrb has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_wready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wdata has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wlast has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bresp has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awburst has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awaddr has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_awready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_bready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awsize has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awcache has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awprot has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awlen has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/DAQ/FIFO_STATUS_0/fifo_wr_data_count
/DAQ/FIFO_STATUS_0/fifo_rd_data_count
validate_bd_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 7466.559 ; gain = 21.766 ; free physical = 1001 ; free virtual = 16985
make_wrapper -files [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd] -top
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wstrb has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_wready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wdata has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wlast has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bresp has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awburst has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awaddr has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_awready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_bready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awsize has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awcache has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awprot has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awlen has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/DAQ/FIFO_STATUS_0/fifo_wr_data_count
/DAQ/FIFO_STATUS_0/fifo_rd_data_count
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/synth/design_1.v
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/sim/design_1.v
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
reset_run synth_1
reset_run design_1_clk_wiz_0_0_synth_1
reset_run design_1_fifo_generator_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wstrb has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_wready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wdata has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wlast has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bresp has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awburst has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awaddr has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_awready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_bready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awsize has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awcache has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awprot has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awlen has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/DAQ/FIFO_STATUS_0/fifo_wr_data_count
/DAQ/FIFO_STATUS_0/fifo_rd_data_count
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/synth/design_1.v
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/sim/design_1.v
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_100M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block selectio_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block selectio_wiz_1 .
Exporting to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0_1/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
Generated Block Design Tcl file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0_1/bd_0/hw_handoff/design_1_system_ila_0_0_bd.tcl
Generated Hardware Definition File /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0_1/bd_0/synth/design_1_system_ila_0_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block SeriPara_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block patternFilter_cfg_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block PatterunFilter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/AXIStream_Converter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/AXIS_Converter_cfg_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/axi_dma_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/DMAamount_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/FIFO_STATUS_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/busy_controller_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/fifo_generator_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_1_1/design_1_auto_pc_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/axi_mem_intercon/s00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0_1/design_1_auto_us_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/axi_mem_intercon/s00_couplers/auto_us .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0_1/design_1_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
Generated Block Design Tcl file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
Generated Hardware Definition File /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/synth/design_1.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_pc_1, cache-ID = 9f4ebfa3473de048; cache size = 23.347 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_us_0, cache-ID = 3b4a742e91bea61b; cache size = 23.347 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_pc_0, cache-ID = b483ac5f30e466e2; cache size = 23.347 MB.
[Wed Apr 17 19:35:11 2019] Launched design_1_clk_wiz_0_0_synth_1, design_1_fifo_generator_0_0_synth_1, synth_1...
Run output will be captured here:
design_1_clk_wiz_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_clk_wiz_0_0_synth_1/runme.log
design_1_fifo_generator_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_fifo_generator_0_0_synth_1/runme.log
synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/synth_1/runme.log
[Wed Apr 17 19:35:11 2019] Launched impl_1...
Run output will be captured here: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 7576.973 ; gain = 78.391 ; free physical = 832 ; free virtual = 16867
file copy -force /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/design_1_wrapper.sysdef /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
launch_sdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
regenerate_bd_layout
save_bd_design
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
exit
INFO: [Common 17-206] Exiting Vivado at Thu Apr 18 23:40:22 2019...