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#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Thu Apr 18 23:42:13 2019
# Process ID: 3320
# Current directory: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01
# Command line: vivado DAQ_socket_loopback_01.xpr
# Log file: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/vivado.log
# Journal file: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/vivado.jou
#-----------------------------------------------------------
start_gui
open_project DAQ_socket_loopback_01.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/ip_repo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/onishi/Xilinx/Vivado/2017.4/data/ip'.
open_project: Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 6274.844 ; gain = 194.664 ; free physical = 11824 ; free virtual = 21374
update_compile_order -fileset sources_1
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_100M
Adding cell -- xilinx.com:ip:selectio_wiz:5.1 - selectio_wiz_0
Adding cell -- xilinx.com:ip:clk_wiz:5.4 - clk_wiz_0
Adding cell -- xilinx.com:ip:selectio_wiz:5.1 - selectio_wiz_1
Adding cell -- xilinx.com:ip:system_ila:1.1 - system_ila_0
Adding cell -- xilinx.com:module_ref:SeriPara:1.0 - SeriPara_0
Adding cell -- user.org:user:patternFilter_cfg:1.0 - patternFilter_cfg_0
Adding cell -- xilinx.com:module_ref:PatterunFilter:1.0 - PatterunFilter_0
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_wiz_0/clk_out2(clk) and /SeriPara_0/clk_in(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_wiz_0/clk_out2(clk) and /PatterunFilter_0/clk_in(undef)
Adding cell -- user.org:user:AXIStream_Converter:1.0 - AXIStream_Converter_0
Adding cell -- user.org:user:AXIS_Converter_cfg:1.0 - AXIS_Converter_cfg_0
Adding cell -- xilinx.com:ip:axi_dma:7.1 - axi_dma_0
Adding cell -- user.org:user:DMAamount:1.0 - DMAamount_0
Adding cell -- user.org:user:FIFO_STATUS:1.0 - FIFO_STATUS_0
Adding cell -- xilinx.com:ip:fifo_generator:13.2 - fifo_generator_0
INFO: [xilinx.com:ip:fifo_generator:13.2-5968] /DAQ/fifo_generator_0Executing the post_config_ip from bd
Adding cell -- user.org:user:busy_controller:1.0 - busy_controller_0
Adding cell -- xilinx.com:ip:fifo_generator:13.2 - fifo_generator_1
INFO: [xilinx.com:ip:fifo_generator:13.2-5968] /DAQ/fifo_generator_1Executing the post_config_ip from bd
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding cell -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Successfully read diagram <design_1> from BD file </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd>
launch_sdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
regenerate_bd_layout
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:02:11
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
disconnect_hw_server localhost:3121
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210248A2713F
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s).
WARNING: [Labtools 27-1347] Unable to find Debug Probes file []. Please update hw_device property [PROBES.FILE]
Update of hw_probe objects, will be skipped.
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z020_1 and the probes file(s) .
The device design has 1 ILA core(s) and 0 VIO core(s). The probes file(s) have 0 ILA core(s) and 0 VIO core(s).
Resolution:
1. Reprogram device with the correct programming file and associated probes file(s) OR
2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device.
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
close_hw
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210248A2713F
set_property PROGRAM.FILE {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/design_1_wrapper.bit} [get_hw_devices xc7z020_1]
set_property PROBES.FILE {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/design_1_wrapper.ltx} [get_hw_devices xc7z020_1]
set_property FULL_PROBES.FILE {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/design_1_wrapper.ltx} [get_hw_devices xc7z020_1]
current_hw_device [get_hw_devices xc7z020_1]
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s).
display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-3304] ILA Waveform data saved to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/backup/hw_ila_data_1.ila. Use Tcl command 'import_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}] -trigger_now
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Apr-19 16:17:28
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2019-Apr-19 16:17:28
INFO: [Labtools 27-3304] ILA Waveform data saved to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/backup/hw_ila_data_1.ila. Use Tcl command 'import_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}] -trigger_now
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Apr-19 17:47:22
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2019-Apr-19 17:47:22
INFO: [Labtools 27-3304] ILA Waveform data saved to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/backup/hw_ila_data_1.ila. Use Tcl command 'import_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
save_wave_config {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wcfg}
close_hw
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:02:11
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210248A2713F
set_property PROGRAM.FILE {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/design_1_wrapper.bit} [get_hw_devices xc7z020_1]
set_property PROBES.FILE {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/design_1_wrapper.ltx} [get_hw_devices xc7z020_1]
set_property FULL_PROBES.FILE {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/design_1_wrapper.ltx} [get_hw_devices xc7z020_1]
current_hw_device [get_hw_devices xc7z020_1]
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
INFO: [Labtools 27-2302] Device xc7z020 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s).
display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-3304] ILA Waveform data saved to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/backup/hw_ila_data_1.ila. Use Tcl command 'import_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}] -trigger_now
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Apr-21 12:26:39
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2019-Apr-21 12:26:39
INFO: [Labtools 27-3304] ILA Waveform data saved to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/backup/hw_ila_data_1.ila. Use Tcl command 'import_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
set_property TRIGGER_COMPARE_VALUE eq1'bR [get_hw_probes design_1_i/system_ila_0/inst/probe5_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes design_1_i/system_ila_0/inst/probe5_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Apr-21 12:26:52
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2019-Apr-21 12:27:02
INFO: [Labtools 27-3304] ILA Waveform data saved to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/backup/hw_ila_data_1.ila. Use Tcl command 'import_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Apr-21 12:27:05
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2019-Apr-21 12:27:09
INFO: [Labtools 27-3304] ILA Waveform data saved to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/backup/hw_ila_data_1.ila. Use Tcl command 'import_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Apr-21 12:27:12
wait_on_hw_ila -timeout 0 [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
INFO: [Labtools 27-1965] The ILA core 'hw_ila_1' trigger was stopped by user at 2019-Apr-21 12:27:22
WARNING: [Labtools 27-157] hw_ila [hw_ila_1] stopped. No data to upload.
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}] -trigger_now
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Apr-21 12:27:22
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2019-Apr-21 12:27:22
INFO: [Labtools 27-3304] ILA Waveform data saved to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/backup/hw_ila_data_1.ila. Use Tcl command 'import_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Apr-21 12:27:23
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2019-Apr-21 12:27:39
INFO: [Labtools 27-3304] ILA Waveform data saved to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/backup/hw_ila_data_1.ila. Use Tcl command 'import_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Apr-21 12:27:42
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2019-Apr-21 12:29:12
INFO: [Labtools 27-3304] ILA Waveform data saved to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/backup/hw_ila_data_1.ila. Use Tcl command 'import_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Apr-21 12:29:15
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2019-Apr-21 12:29:31
INFO: [Labtools 27-3304] ILA Waveform data saved to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/backup/hw_ila_data_1.ila. Use Tcl command 'import_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Apr-21 12:29:34
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2019-Apr-21 12:34:28
INFO: [Labtools 27-3304] ILA Waveform data saved to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.hw/backup/hw_ila_data_1.ila. Use Tcl command 'import_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z020_1] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Apr-21 12:34:31
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
startgroup
set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {320.000} CONFIG.MMCM_DIVCLK_DIVIDE {5} CONFIG.MMCM_CLKFBOUT_MULT_F {48.000} CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} CONFIG.MMCM_CLKOUT1_DIVIDE {3} CONFIG.CLKOUT1_JITTER {290.458} CONFIG.CLKOUT1_PHASE_ERROR {301.601} CONFIG.CLKOUT2_JITTER {213.791} CONFIG.CLKOUT2_PHASE_ERROR {301.601}] [get_bd_cells clk_wiz_0]
endgroup
validate_bd_design
WARNING: [BD 41-1781] Updates have been made to one or more nets/interface connections marked for debug.
Debug nets, which are already connected to System ILA IP core in the block-design, will be automatically available for debug in Hardware Manager.
For unconnected Debug nets, please open synthesized design and use 'Set Up Debug' wizard to insert, modify or delete Debug Cores. Failure to do so could result in critical warnings and errors in the implementation flow.
INFO: [Device 21-403] Loading part xc7z020clg484-1
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wstrb has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_wready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wdata has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wlast has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bresp has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awburst has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awaddr has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_awready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_bready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awsize has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awcache has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awprot has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awlen has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/DAQ/FIFO_STATUS_0/fifo_wr_data_count
/DAQ/FIFO_STATUS_0/fifo_rd_data_count
validate_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 7449.367 ; gain = 123.387 ; free physical = 520 ; free virtual = 19811
make_wrapper -files [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd] -top
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wstrb has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_wready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wdata has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wlast has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bresp has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awburst has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awaddr has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_awready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_bready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awsize has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awcache has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awprot has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awlen has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/DAQ/FIFO_STATUS_0/fifo_wr_data_count
/DAQ/FIFO_STATUS_0/fifo_rd_data_count
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/synth/design_1.v
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/sim/design_1.v
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
reset_run synth_1
reset_run design_1_clk_wiz_0_0_synth_1
reset_run design_1_fifo_generator_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wstrb has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_wready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wdata has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_wlast has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_bresp has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awburst has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awaddr has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_mem_intercon/S00_AXI_awready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_bready has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awvalid has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awsize has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awcache has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awprot has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
WARNING: [BD 41-1271] The connection to the pin: /DAQ/axi_dma_0/m_axi_s2mm_awlen has been overridden by the user. This pin will not be connected as a part of the interface connection: axi_dma_0_M_AXI_S2MM
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/DAQ/FIFO_STATUS_0/fifo_wr_data_count
/DAQ/FIFO_STATUS_0/fifo_rd_data_count
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/synth/design_1.v
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/DAQ/FIFO_STATUS_0/fifo_data_count'(32) to net 'axis_data_fifo_0_axis_data_count'(17) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/sim/design_1.v
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_c28c1ac4.ui>
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_100M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block selectio_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block selectio_wiz_1 .
Exporting to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0_1/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
Generated Block Design Tcl file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0_1/bd_0/hw_handoff/design_1_system_ila_0_0_bd.tcl
Generated Hardware Definition File /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0_1/bd_0/synth/design_1_system_ila_0_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block SeriPara_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block patternFilter_cfg_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block PatterunFilter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/AXIStream_Converter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/AXIS_Converter_cfg_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/axi_dma_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/DMAamount_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/FIFO_STATUS_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/busy_controller_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/fifo_generator_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_1_1/design_1_auto_pc_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/axi_mem_intercon/s00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0_1/design_1_auto_us_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block DAQ/axi_mem_intercon/s00_couplers/auto_us .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0_1/design_1_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
Generated Block Design Tcl file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
Generated Hardware Definition File /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/synth/design_1.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_pc_1, cache-ID = 9f4ebfa3473de048; cache size = 24.262 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_us_0, cache-ID = 3b4a742e91bea61b; cache size = 24.262 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_pc_0, cache-ID = b483ac5f30e466e2; cache size = 24.262 MB.
[Sun Apr 21 13:50:46 2019] Launched design_1_clk_wiz_0_0_synth_1, design_1_fifo_generator_0_0_synth_1, synth_1...
Run output will be captured here:
design_1_clk_wiz_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_clk_wiz_0_0_synth_1/runme.log
design_1_fifo_generator_0_0_synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/design_1_fifo_generator_0_0_synth_1/runme.log
synth_1: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/synth_1/runme.log
[Sun Apr 21 13:50:46 2019] Launched impl_1...
Run output will be captured here: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 7628.969 ; gain = 101.816 ; free physical = 278 ; free virtual = 19673
launch_sdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
file copy -force /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.runs/impl_1/design_1_wrapper.sysdef /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
launch_sdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk -hwspec /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
ERROR: [Xicom 50-38] xicom: Unable to connect to debug core(s) on the target device. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210248A2713F