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#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Tue Apr 16 18:36:25 2019
# Process ID: 4698
# Current directory: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01
# Command line: vivado
# Log file: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/vivado.log
# Journal file: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/vivado.jou
#-----------------------------------------------------------
start_gui
create_project DAQ_socket_loopback_01 . -part xc7z020clg484-1
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/onishi/Xilinx/Vivado/2017.4/data/ip'.
set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
add_files -norecurse {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/32bitConverter.v /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/PatterunFilter.v /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/DSinput.v /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/SeriPara.v /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/IBUFDS.v}
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
export_ip_user_files -of_objects [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/32bitConverter.v] -no_script -reset -force -quiet
remove_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/32bitConverter.v
remove_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/32bitConverter.v
WARNING: [Vivado 12-818] No files matched '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/new/32bitConverter.v'
add_files -norecurse /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/bd/design_1/design_1.bd
CRITICAL WARNING: [filemgmt 20-1381] The sub-design source file can not be added to the current project since there is an overlap between the sub-design directory structure and the project directory structure. Sources representing Embedded/DSP/IP sub-designs need to be located in their own directory structure. Allowing the project directory structure to overlap with the sub-design directory structure will cause errors later in the flows for any operation that requires the sub-design to be local to the project. Examples of these operations are: copying the sub-design to the project locally, project archive, project save as etc.
Please move either the project or the Embedded/DSP/IP sub-design directory structure to a different location so that there are no more overlaps, and then try adding the sub-design source to this project again. If a remote sub-design is being added to an existing project, it is recommended that the sub-design directory tree be placed completely outside the project directory structure, the sub-design root file added to the project, and then imported into the project.
project location: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01
sub-design source location: /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/bd/design_1/design_1.bd
CRITICAL WARNING: [Vivado 12-1464] The source file '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.src/sources_1/bd/design_1/design_1.bd' cannot be added to the fileset 'sources_1'.
create_bd_design "design_1"
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd>
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
update_compile_order -fileset sources_1
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
set_property ip_repo_paths /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/ip_repo [current_project]
update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/ip_repo'.
close_bd_design [get_bd_designs design_1]
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
Successfully read diagram <design_1> from BD file </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd>
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
generate_target all [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd]
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd>
Wrote : </mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/synth/design_1.v
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/sim/design_1.v
VHDL Output written to : /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
Exporting to file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
Generated Block Design Tcl file /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
Generated Hardware Definition File /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/synth/design_1.hwdef
export_ip_user_files -of_objects [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd]
export_simulation -of_objects [get_files /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd] -directory /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.ip_user_files/sim_scripts -ip_user_files_dir /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.ip_user_files -ipstatic_source_dir /mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.ip_user_files/ipstatic -lib_map_path [list {modelsim=/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.cache/compile_simlib/modelsim} {questa=/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.cache/compile_simlib/questa} {ies=/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.cache/compile_simlib/ies} {vcs=/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.cache/compile_simlib/vcs} {riviera=/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet
open_bd_design {/mnt/HDD1/onishi/Vivado_Project/work/DAQ_socket_loopback_01/DAQ_socket_loopback_01.srcs/sources_1/bd/design_1/design_1.bd}
exit
INFO: [Common 17-206] Exiting Vivado at Wed Apr 17 13:56:03 2019...