- Jan 14, 2021
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Evaldas Juska authored
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- Jan 13, 2021
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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- Jan 12, 2021
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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- Jan 11, 2021
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Evaldas Juska authored
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- Jan 09, 2021
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Evaldas Juska authored
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- Jan 08, 2021
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Evaldas Juska authored
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Evaldas Juska authored
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- Jan 07, 2021
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Evaldas Juska authored
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Evaldas Juska authored
put back the PYTHONPATH stuff and decrease NJOBS from 24 to 12 in order not to blow up machines with not much RAM
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Evaldas Juska authored
fixed a bug related to address width mismatch in the axi-ipb bridge (interestingly this has only been flagged as an error in vivado 2019.2)
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- Jan 06, 2021
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Evaldas Juska authored
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- Jan 04, 2021
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Evaldas Juska authored
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- Dec 21, 2020
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
also register the MISO signals, not only MOSI (this was actually causing the FSM to run twice for each read and write)
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Evaldas Juska authored
add a few global slow control monitoring registers, will use as a workaround in CVP13 to check if the last transaction was a fail or success for now
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Evaldas Juska authored
add a few global slow control monitoring registers, will use as a workaround in CVP13 to check if the last transaction was a fail or success for now
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- Dec 19, 2020
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Evaldas Juska authored
Initial CVP13 documentation added. PCIe Device ID set to 0xBEFE :) also board ID register set to 0xBEFE
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- Dec 18, 2020
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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- Dec 17, 2020
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
axi-ipbus bridge timeout set to 3000 cycles (60us @ 50MHz), ipb-slave set to 2000 cycles (40us @ 50MHz)
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Evaldas Juska authored
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Evaldas Juska authored
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Evaldas Juska authored
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