Skip to content
Snippets Groups Projects
Commit a0b3d623 authored by Rocco Ardino's avatar Rocco Ardino :registered:
Browse files

Add copy of calo output and prepare project for p2gt stuff

parent 3228b700
No related branches found
No related tags found
1 merge request!84L1calo add crc error flag
Pipeline #8566379 passed
Stage: triggers
Pipeline: scouting-preprocessor

#8566382

    Pipeline: scouting-preprocessor

    #8566381

      Pipeline: scouting-preprocessor

      #8566380

        Expand all Hide whitespace changes
        Inline Side-by-side
        Showing
        with 2914 additions and 1 deletion
        boards/vcu128/addrtab/address_table_calop2gt.json 0 → 100644
        + 178
        − 0
        View file @ a0b3d623
        {
        "vcu128_calop2gt": {
        "driver": "/dev/xpci",
        "vendorId" : "0x10dc",
        "deviceId" : "0x01b5",
        "index" : 1,
        "hal_addrtable" : "address_map_vcu128_calop2gt.dat",
        "hal_addrpath" : "/opt/l1scouting-hardware/bitfiles/currently_used/",
        "board_status" : "HALTED",
        "registers": {
        "general" : {
        "scouting_ctrl_register_offset" : { "metric": "gauge" , "writable": false, "exposable": false },
        "scouting_moni_register_offset" : { "metric": "gauge" , "writable": false, "exposable": false },
        "algo_version" : { "metric": "gauge" , "writable": true , "exposable" : true },
        "fw_type" : { "metric": "gauge" , "writable": true , "exposable" : true },
        "freq_clk_x0y0" : { "metric": "gauge" , "writable": true , "exposable" : true },
        "freq_clk_x0y1" : { "metric": "gauge" , "writable": true , "exposable" : true },
        "freq_clk_x0y2" : { "metric": "gauge" , "writable": true , "exposable" : true },
        "freq_clk_x0y3" : { "metric": "gauge" , "writable": true , "exposable" : true },
        "freq_clk_x0y4" : { "metric": "gauge" , "writable": true , "exposable" : true },
        "freq_clk_x0y5" : { "metric": "gauge" , "writable": true , "exposable" : true },
        "freq_clk_x0y7" : { "metric": "gauge" , "writable": true , "exposable" : true },
        "freq_clk_x0y8" : { "metric": "gauge" , "writable": true , "exposable" : true },
        "freq_clk_x0y10" : { "metric": "gauge" , "writable": true , "exposable" : true },
        "freq_clk_x0y11" : { "metric": "gauge" , "writable": true , "exposable" : true },
        "freq_clk_axi" : { "metric": "gauge" , "writable": true , "exposable" : true }
        },
        "calo" : {
        "scouting_ctrl_register_offset" : { "metric": "gauge" , "writable": false, "exposable": false },
        "stream_enable_mask" : { "metric": "gauge" , "writable": true , "exposable": true },
        "local_reset" : { "metric": "gauge" , "writable": true , "exposable": true },
        "link_map" : { "metric": "gauge" , "writable": true , "exposable": true , "copies": 8 },
        "disable_zs_jet" : { "metric": "gauge" , "writable": true , "exposable": true },
        "disable_zs_eg" : { "metric": "gauge" , "writable": true , "exposable": true },
        "disable_zs_sum" : { "metric": "gauge" , "writable": true , "exposable": true },
        "disable_zs_tau" : { "metric": "gauge" , "writable": true , "exposable": true },
        "et_cut_jet" : { "metric": "gauge" , "writable": true , "exposable": true },
        "et_cut_eg" : { "metric": "gauge" , "writable": true , "exposable": true },
        "et_cut_sum" : { "metric": "gauge" , "writable": true , "exposable": true },
        "et_cut_tau" : { "metric": "gauge" , "writable": true , "exposable": true },
        "orbits_per_packet" : { "metric": "gauge" , "writable": true , "exposable": true },
        "orbits_per_chunk" : { "metric": "gauge" , "writable": true , "exposable": true },
        "wait_for_oc1" : { "metric": "gauge" , "writable": true , "exposable": true },
        "enable_data_gen" : { "metric": "gauge" , "writable": true , "exposable": true },
        "gen_orbit_full_length" : { "metric": "gauge" , "writable": true , "exposable": true },
        "gen_orbit_data_length" : { "metric": "gauge" , "writable": true , "exposable": true },
        "disable_reshape" : { "metric": "gauge" , "writable": true , "exposable": true },
        "scouting_source_id" : { "metric": "gauge" , "writable": true , "exposable": true , "copies": 4 },
        "scouting_moni_register_offset" : { "metric": "gauge" , "writable": false, "exposable": false },
        "rx_byte_is_aligned_info" : { "metric": "gauge" , "writable": false, "exposable": true },
        "gt_power_good_info" : { "metric": "gauge" , "writable": false, "exposable": false },
        "cdr_stable_info" : { "metric": "gauge" , "writable": false, "exposable": true },
        "gt_tx_reset_done_info" : { "metric": "gauge" , "writable": false, "exposable": false },
        "gt_rx_reset_done_info" : { "metric": "gauge" , "writable": false, "exposable": false },
        "gt_reset_tx_pll_datapath_info" : { "metric": "gauge" , "writable": false, "exposable": false },
        "gt_reset_tx_datapath_info" : { "metric": "gauge" , "writable": false, "exposable": false },
        "gt_reset_rx_datapath_info" : { "metric": "gauge" , "writable": false, "exposable": false },
        "init_done_info" : { "metric": "gauge" , "writable": false, "exposable": false },
        "waiting_for_orbit_end_info" : { "metric": "gauge" , "writable": false, "exposable": false },
        "packager_seen_orbits" : { "metric": "counter", "writable": false, "exposable": true , "copies": 4 },
        "packager_dropped_orbits" : { "metric": "counter", "writable": false, "exposable": true , "copies": 4 },
        "orbit_length_bxs" : { "metric": "gauge" , "writable": false, "exposable": true , "copies": 4 },
        "axi_backpressure_seen_info" : { "metric": "gauge" , "writable": false, "exposable": true },
        "orbit_exceeds_size_info" : { "metric": "gauge" , "writable": false, "exposable": true },
        "autorealigns_total" : { "metric": "counter", "writable": false, "exposable": true },
        "algo_version" : { "metric": "gauge" , "writable": false, "exposable": true },
        "fw_type" : { "metric": "gauge" , "writable": false, "exposable": true },
        "freq_clk_rec" : { "metric": "gauge" , "writable": false, "exposable": true , "copies": 8 },
        "crc_error_counter" : { "metric": "gauge" , "writable": false, "exposable": true , "copies": 8 }
        },
        "calocopy" : {
        "scouting_ctrl_register_offset" : { "metric": "gauge" , "writable": false, "exposable": false },
        "orbits_per_packet" : { "metric": "gauge" , "writable": true , "exposable": true },
        "orbits_per_chunk" : { "metric": "gauge" , "writable": true , "exposable": true },
        "wait_for_oc1" : { "metric": "gauge" , "writable": true , "exposable": true },
        "scouting_source_id" : { "metric": "gauge" , "writable": true , "exposable": true , "copies": 8 },
        "scouting_moni_register_offset" : { "metric": "gauge" , "writable": false, "exposable": false },
        "packager_seen_orbits" : { "metric": "counter", "writable": false, "exposable": true , "copies": 8 },
        "packager_dropped_orbits" : { "metric": "counter", "writable": false, "exposable": true , "copies": 8 },
        "orbit_length_bxs" : { "metric": "gauge" , "writable": false, "exposable": true , "copies": 8 },
        "autorealigns_total" : { "metric": "counter", "writable": false, "exposable": true },
        "algo_version" : { "metric": "gauge" , "writable": false, "exposable": true },
        "fw_type" : { "metric": "gauge" , "writable": false, "exposable": true }
        }
        },
        "actions": [
        "initialize",
        "reset",
        "configure",
        "start",
        "stop",
        "halt",
        "health_detailed",
        "health_input",
        "health_clock",
        "health_data",
        "update_board_config",
        "dump_board_config",
        "enable_data_gen",
        "disable_data_gen",
        "enable_stream_reshape",
        "disable_stream_reshape",
        "reset_hbm",
        "reset_and_configure_daq_transceiver",
        "configure_daq_transceiver",
        "configure_ip_pars",
        "configure_tcp_pars",
        "configure_daq_serdes",
        "send_arp",
        "open_connection",
        "close_connection",
        "enable_input_links",
        "disable_input_links",
        "remap_trigger_input_links"
        ],
        "module_offsets": {
        "general_item" : [0],
        "hbm_item" : [0],
        "tcp_stream" : [0, 424, 848, 1272, 1696, 2120, 2544, 2968, 3392, 3816, 4240, 4664, 5088, 5512],
        "daq_eth_100gb" : [0 , 648, 1296],
        "scouting_registers" : [0]
        },
        "parameters": {
        "enabled_systems" : ["calo", "calocopy"],
        "available_systems" : {
        "calo" : {
        "source_idx" : 0,
        "n_input_links" : 8,
        "n_regions" : 2,
        "input_link_map" : [0,1,2,3, 4,5,6,7],
        "input_link_disable" : [0,0,0,0, 0,0,0,0],
        "n_daq_units" : 1,
        "n_tcp_streams" : [4],
        "tcp_stream_map" : [0,1,2,3],
        "daq_map" : [0]
        },
        "calocopy" : {
        "source_idx" : 1,
        "n_input_links" : 8,
        "n_regions" : 2,
        "input_link_map" : [0,1,2,3, 4,5,6,7],
        "input_link_disable" : [0,0,0,0, 0,0,0,0],
        "n_daq_units" : 2,
        "n_tcp_streams" : [4, 4],
        "tcp_stream_map" : [4,5,6,7, 8,9,10,11],
        "daq_map" : [1,2]
        }
        },
        "orbits_per_packet" : 1,
        "orbits_per_chunk" : 4096,
        "wait_for_oc1" : 0,
        "daq_enable" : [1, 1, 1],
        "tcp_daq_map" : [0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2],
        "tcp_stream_enable" : [1,1,1,1, 1,1,1,1, 1,1,1,1],
        "source_ip" : ["10.177.128.194", "10.177.128.195", "10.177.128.196"],
        "dest_ip" : ["10.177.128.176", "10.177.128.176", "10.177.128.176"],
        "source_port" : [[10000, 10010, 10020, 10030], [10000, 10010, 10020, 10030], [10000, 10010, 10020, 10030]],
        "dest_port" : [[10000, 10000, 10000, 10000], [10000, 10000, 10000, 10000], [10000, 10000, 10000, 10000]],
        "eth_100gb_tcp_win" : 1024,
        "eth_100gb_ctrl_scale_def" : 1,
        "eth_100gb_ctrl_mss_def_def" : 8960,
        "eth_100gb_ctrl_timestamp_def" : 0,
        "eth_100gb_ctrl_timestamp_reply_def" : 0,
        "eth_100gb_ctrl_congwind_def" : 1048576,
        "eth_100gb_ctrl_timer_rtt_def" : 312500,
        "eth_100gb_ctrl_timer_rtt_sync_def" : 312500000,
        "eth_100gb_ctrl_timer_persist_def" : 625000,
        "eth_100gb_ctrl_thresold_retrans_def" : 3,
        "eth_100gb_ctrl_rexmt_cwnd_sh_def" : 6
        },
        "health_check" : {
        "freq_clk_rec" : { "expected_val" : 250000000 },
        "freq_clk_eth" : { "expected_val" : 322265625 },
        "freq_clk_hbm" : { "expected_val" : 250000000 },
        "freq_clk_axi" : { "expected_val" : 62500000 }
        }
        }
        }
        \ No newline at end of file
        boards/vcu128/addrtab/pyhal/items/copy_scouting_pipeline_registers.txt 0 → 100644
        + 66
        − 0
        View file @ a0b3d623
        -- Name SubName Data_Mask read_write Comment
        -- Setting Setting_b0 xffffffffffffffff rw
        --------------------------------------------------------------------------------------------------------------------------------------
        copy_scouting_ctrl_register_offset copy_scouting_ctrl_register_offset x00000000ffffffff r
        copy_orbits_per_packet copy_orbits_per_packet x000000000000ffff rw
        copy_orbits_per_chunk copy_orbits_per_chunk x00000000000fffff rw
        copy_wait_for_oc1 copy_wait_for_oc1 x0000000000000001 rw
        copy_scouting_source_id_00 copy_scouting_source_id_00 x00000000ffffffff rw
        copy_scouting_source_id_01 copy_scouting_source_id_01 x00000000ffffffff rw
        copy_scouting_source_id_02 copy_scouting_source_id_02 x00000000ffffffff rw
        copy_scouting_source_id_03 copy_scouting_source_id_03 x00000000ffffffff rw
        copy_scouting_source_id_04 copy_scouting_source_id_04 x00000000ffffffff rw
        copy_scouting_source_id_05 copy_scouting_source_id_05 x00000000ffffffff rw
        copy_scouting_source_id_06 copy_scouting_source_id_06 x00000000ffffffff rw
        copy_scouting_source_id_07 copy_scouting_source_id_07 x00000000ffffffff rw
        copy_scouting_source_id_08 copy_scouting_source_id_08 x00000000ffffffff rw
        copy_scouting_source_id_09 copy_scouting_source_id_09 x00000000ffffffff rw
        copy_scouting_source_id_10 copy_scouting_source_id_10 x00000000ffffffff rw
        copy_scouting_source_id_11 copy_scouting_source_id_11 x00000000ffffffff rw
        copy_scouting_moni_register_offset copy_scouting_moni_register_offset x00000000ffffffff r
        copy_packager_seen_orbits_00 copy_packager_seen_orbits_00 x00000000ffffffff r
        copy_packager_seen_orbits_01 copy_packager_seen_orbits_01 x00000000ffffffff r
        copy_packager_seen_orbits_02 copy_packager_seen_orbits_02 x00000000ffffffff r
        copy_packager_seen_orbits_03 copy_packager_seen_orbits_03 x00000000ffffffff r
        copy_packager_seen_orbits_04 copy_packager_seen_orbits_04 x00000000ffffffff r
        copy_packager_seen_orbits_05 copy_packager_seen_orbits_05 x00000000ffffffff r
        copy_packager_seen_orbits_06 copy_packager_seen_orbits_06 x00000000ffffffff r
        copy_packager_seen_orbits_07 copy_packager_seen_orbits_07 x00000000ffffffff r
        copy_packager_seen_orbits_08 copy_packager_seen_orbits_08 x00000000ffffffff r
        copy_packager_seen_orbits_09 copy_packager_seen_orbits_09 x00000000ffffffff r
        copy_packager_seen_orbits_10 copy_packager_seen_orbits_10 x00000000ffffffff r
        copy_packager_seen_orbits_11 copy_packager_seen_orbits_11 x00000000ffffffff r
        copy_packager_dropped_orbits_00 copy_packager_dropped_orbits_00 x00000000ffffffff r
        copy_packager_dropped_orbits_01 copy_packager_dropped_orbits_01 x00000000ffffffff r
        copy_packager_dropped_orbits_02 copy_packager_dropped_orbits_02 x00000000ffffffff r
        copy_packager_dropped_orbits_03 copy_packager_dropped_orbits_03 x00000000ffffffff r
        copy_packager_dropped_orbits_04 copy_packager_dropped_orbits_04 x00000000ffffffff r
        copy_packager_dropped_orbits_05 copy_packager_dropped_orbits_05 x00000000ffffffff r
        copy_packager_dropped_orbits_06 copy_packager_dropped_orbits_06 x00000000ffffffff r
        copy_packager_dropped_orbits_07 copy_packager_dropped_orbits_07 x00000000ffffffff r
        copy_packager_dropped_orbits_08 copy_packager_dropped_orbits_08 x00000000ffffffff r
        copy_packager_dropped_orbits_09 copy_packager_dropped_orbits_09 x00000000ffffffff r
        copy_packager_dropped_orbits_10 copy_packager_dropped_orbits_10 x00000000ffffffff r
        copy_packager_dropped_orbits_11 copy_packager_dropped_orbits_11 x00000000ffffffff r
        copy_orbit_length_bxs_00 copy_orbit_length_bxs_00 x00000000ffffffff r
        copy_orbit_length_bxs_01 copy_orbit_length_bxs_01 x00000000ffffffff r
        copy_orbit_length_bxs_02 copy_orbit_length_bxs_02 x00000000ffffffff r
        copy_orbit_length_bxs_03 copy_orbit_length_bxs_03 x00000000ffffffff r
        copy_orbit_length_bxs_04 copy_orbit_length_bxs_04 x00000000ffffffff r
        copy_orbit_length_bxs_05 copy_orbit_length_bxs_05 x00000000ffffffff r
        copy_orbit_length_bxs_06 copy_orbit_length_bxs_06 x00000000ffffffff r
        copy_orbit_length_bxs_07 copy_orbit_length_bxs_07 x00000000ffffffff r
        copy_orbit_length_bxs_08 copy_orbit_length_bxs_08 x00000000ffffffff r
        copy_orbit_length_bxs_09 copy_orbit_length_bxs_09 x00000000ffffffff r
        copy_orbit_length_bxs_10 copy_orbit_length_bxs_10 x00000000ffffffff r
        copy_orbit_length_bxs_11 copy_orbit_length_bxs_11 x00000000ffffffff r
        copy_autorealigns_total copy_autorealigns_total x00000000ffffffff r
        copy_algo_version copy_algo_version x0000000000ffffff r
        copy_fw_type copy_fw_type x00000000000000ff r
        boards/vcu128/addrtab/pyhal/vcu128_calop2gt_address_structure.txt 0 → 100644
        + 16
        − 0
        View file @ a0b3d623
        -- This file give the structure of the different address files used
        -- first module should should be oin level 0
        -- Same module on same level should follow (no other module between a same)
        -- Actually only 2 levels max.
        -- Each primary address table should preceed by 1 +
        -- If inside the primary block there is 1 or more seconday block it should be preceed by ++
        -- the 0 is used to specify PCI configuration
        0 pcie_configuration 1
        + general_item 1
        + hbm_item 1
        + tcp_stream 14
        + daq_eth_100gb 3
        + generic_scouting_registers 1
        + calo_scouting_pipeline_registers 1
        + copy_scouting_pipeline_registers 1
        boards/vcu128/firmware/ucf/vcu128_calop2gt_io_timing.xdc 0 → 100644
        + 88
        − 0
        View file @ a0b3d623
        create_clock -period 10.000 -name CLK1_100MHZ_P [get_ports CLK1_100MHZ_P]
        create_clock -period 10.000 -name HBM_clk_ref_p [get_ports HBM_clk_ref_p]
        create_generated_clock -name ena_clock_i2c -source [get_pins pll_inst/inst/mmcme4_adv_inst/CLKOUT0] -divide_by 64 [get_pins ena_clock_i2c_reg/Q]
        create_clock -period 10.000 -name PCIE_clk_p [get_ports PCIE_clk_p]
        set_false_path -from [get_ports PCIE_rst]
        set_false_path -to [get_ports ClockGen_MAIN_RESET]
        set_false_path -to [get_ports sysMon_i2c_sda]
        set_false_path -to [get_ports sysMon_i2c_sclk]
        set_false_path -to [get_ports ClockGen_MAIN_SDA]
        set_false_path -to [get_ports ClockGen_MAIN_SCL]
        set_false_path -to [get_ports FireFly_MAIN_SDA]
        set_false_path -to [get_ports FireFly_MAIN_SCL]
        set_false_path -to [get_ports QSFP_MAIN_SDA]
        set_false_path -to [get_ports QSFP_MAIN_SCL]
        set_false_path -to [get_ports SN_MAIN_SDA]
        set_false_path -to [get_ports SN_MAIN_SCL]
        set_multicycle_path -setup -to [get_ports sysMon_i2c_sclk] 60
        set_multicycle_path -hold -to [get_ports sysMon_i2c_sclk] 3
        set_multicycle_path -setup -to [get_ports ClockGen_MAIN_SCL] 60
        set_multicycle_path -hold -to [get_ports ClockGen_MAIN_SCL] 3
        set_multicycle_path -setup -to [get_ports FireFly_MAIN_SCL] 60
        set_multicycle_path -hold -to [get_ports FireFly_MAIN_SCL] 3
        set_multicycle_path -setup -to [get_ports QSFP_MAIN_SCL] 60
        set_multicycle_path -hold -to [get_ports QSFP_MAIN_SCL] 3
        set_multicycle_path -setup -to [get_ports SN_MAIN_SCL] 60
        set_multicycle_path -hold -to [get_ports SN_MAIN_SCL] 3
        set_multicycle_path -setup -to [get_ports ClockGen_MAIN_SDA] 60
        set_multicycle_path -hold -to [get_ports ClockGen_MAIN_SDA] 3
        set_multicycle_path -setup -to [get_ports FireFly_MAIN_SDA] 60
        set_multicycle_path -hold -to [get_ports FireFly_MAIN_SDA] 3
        set_multicycle_path -setup -to [get_ports QSFP_MAIN_SDA] 60
        set_multicycle_path -hold -to [get_ports QSFP_MAIN_SDA] 3
        set_multicycle_path -setup -to [get_ports SN_MAIN_SDA] 60
        set_multicycle_path -hold -to [get_ports SN_MAIN_SDA] 3
        set_multicycle_path -setup -to [get_ports sysMon_i2c_sda] 60
        set_false_path -to [get_ports {Flash_add[*]}]
        set_false_path -to [get_ports GPIO_LED_*_LS]
        #
        set_max_delay -to [get_ports GPIO_LED_0_LS] 20.000
        set_max_delay -to [get_ports GPIO_LED_1_LS] 20.000
        set_max_delay -to [get_ports GPIO_LED_2_LS] 20.000
        set_max_delay -to [get_ports GPIO_LED_3_LS] 20.000
        set_max_delay -to [get_ports GPIO_LED_4_LS] 20.000
        set_max_delay -to [get_ports GPIO_LED_5_LS] 20.000
        set_max_delay -to [get_ports GPIO_LED_6_LS] 20.000
        set_max_delay -to [get_ports GPIO_LED_7_LS] 20.000
        set_max_delay -to [get_ports QSFP_*_MODSEL] 20.000
        set_max_delay -to [get_ports QSFP_*_RESETL] 20.000
        set_max_delay -to [get_ports QSFP_*_LPMODE] 20.000
        set_false_path -from [get_ports QSFP_*_MODPRSL]
        set_false_path -from [get_ports QSFP_*_INTL]
        create_clock -period 10000.000 -name POWER_MAIN_SCL_virtual
        create_clock -period 10000.000 -name SN_MAIN_SCL_virtual
        create_clock -period 10000.000 -name ClockGen_MAIN_SCL_virtual
        create_clock -period 10000.000 -name HMC_MAIN_SCL_virtual
        create_clock -period 10000.000 -name FireFly_MAIN_SCL_virtual
        create_clock -period 10000.000 -name QSFP_MAIN_SCL_virtual
        #
        set_false_path -to [get_ports ClockGen_*_rst_n]
        create_clock -name clk_mgtrefclk0_x0y0_p -period 6.4 [get_ports mgtrefclk0_x0y0_p]
        create_clock -name clk_mgtrefclk0_x0y1_p -period 6.4 [get_ports mgtrefclk0_x0y1_p]
        create_clock -name clk_mgtrefclk0_x0y2_p -period 6.4 [get_ports mgtrefclk0_x0y2_p]
        create_clock -name clk_mgtrefclk0_x0y3_p -period 6.4 [get_ports mgtrefclk0_x0y3_p]
        create_clock -name clk_mgtrefclk0_x0y4_p -period 6.4 [get_ports mgtrefclk0_x0y4_p]
        create_clock -name clk_mgtrefclk0_x0y5_p -period 6.4 [get_ports mgtrefclk0_x0y5_p]
        create_clock -name clk_mgtrefclk0_x0y11_p -period 6.4 [get_ports mgtrefclk0_x0y11_p]
        create_clock -period 3.103 -name mgtrefclk0_x0y7_p -waveform {0.000 1.552} [get_ports mgtrefclk0_x0y7_p]
        create_clock -period 3.103 -name mgtrefclk0_x0y8_p -waveform {0.000 1.552} [get_ports mgtrefclk0_x0y8_p]
        create_clock -period 3.103 -name mgtrefclk0_x0y10_p -waveform {0.000 1.552} [get_ports mgtrefclk0_x0y10_p]
        \ No newline at end of file
        boards/vcu128/pipelines/firmware/hdl/calo_scouting_pipeline.vhd
        + 13
        − 1
        View file @ a0b3d623
        ......@@ -112,7 +112,13 @@ entity calo_scouting_pipeline is
        o_packager_Fragment_Header_ila_sync : out packager_tdata(N_HBM_PORTS - 1 downto 0);
        o_packager_Write_Fragment_Header_ila_sync : out packager_tbit(N_HBM_PORTS - 1 downto 0);
        o_packager_Orbit_Header_ila_sync : out packager_tdata(N_HBM_PORTS - 1 downto 0);
        o_packager_Write_Orbit_Header_ila_sync : out packager_tbit(N_HBM_PORTS - 1 downto 0)
        o_packager_Write_Orbit_Header_ila_sync : out packager_tbit(N_HBM_PORTS - 1 downto 0);
        ---- copy of packager inputs
        o_d_package : out TStream_aframe(N_HBM_PORTS - 1 downto 0);
        o_d_ctrl_package : out TStream_acontrol(N_HBM_PORTS - 1 downto 0);
        o_autorealign_counter : out unsigned(63 downto 0);
        o_rst_packager : out std_logic
        );
        end calo_scouting_pipeline;
        ......@@ -879,6 +885,12 @@ begin
        o_packager_Write_Fragment_Header_ila_sync <= packager_Write_Fragment_Header;
        o_packager_Orbit_Header_ila_sync <= packager_Orbit_Header;
        o_packager_Write_Orbit_Header_ila_sync <= packager_Write_Orbit_Header;
        ---- copy of packager inputs
        o_d_package <= d_package;
        o_d_ctrl_package <= d_ctrl_package;
        o_autorealign_counter <= autorealign_counter;
        o_rst_packager <= rst_packager;
        ---------------------------------------------------------------------------
        ......
        boards/vcu128/pipelines/firmware/hdl/copy_scouting_pipeline.vhd 0 → 100644
        + 444
        − 0
        View file @ a0b3d623
        This diff is collapsed.
        boards/vcu128/top/firmware/hdl/vcu128_calop2gt_top.vhd 0 → 100644
        + 2019
        − 0
        View file @ a0b3d623
        This diff is collapsed.
        projects/vcu128/calop2gt/firmware/cfg/top_scouting_calop2gt.dep 0 → 100644
        + 16
        − 0
        View file @ a0b3d623
        include -c boards/vcu128 vcu128_tcp.dep
        src --vhdl2008 -c boards/vcu128/top vcu128_calop2gt_top.vhd
        src --vhdl2008 -c boards/vcu128/pipelines calo_scouting_pipeline.vhd
        src --vhdl2008 -c boards/vcu128/pipelines copy_scouting_pipeline.vhd
        # src --vhdl2008 -c boards/vcu128/pipelines p2gt_scouting_pipeline.vhd
        src --vhdl2008 -c boards/vcu128 calo_stream_reshape.vhd
        src --vhdl2008 -c boards/vcu128/dth address_table_vcu128.vhd
        src --vhdl2008 -c components/data_reduction zs_calo.vhd
        src --vhdl2008 -c components/data_reduction suppress_calibration_data_no_reg.vhd
        src --vhdl2008 -c projects/vcu128/common top_decl_tcp.vhd
        src --vhdl2008 algo_decl_calop2gt.vhd
        src --cd ../../../../../boards/vcu128/firmware/ucf vcu128_calop2gt_io_timing.xdc
        setup -c boards/vcu128 build.tcl
        projects/vcu128/calop2gt/firmware/hdl/algo_decl_calop2gt.vhd 0 → 100644
        + 17
        − 0
        View file @ a0b3d623
        -- algo_decl for CALO+P2GT scouting
        --
        -- Constants for the whole device
        --
        -- R. Ardino March 2024
        library IEEE;
        use IEEE.STD_LOGIC_1164.all;
        package algo_decl is
        constant FW_TYPE : std_logic_vector(7 downto 0) := X"10";
        constant N_REGION : positive := 2;
        constant N_STREAM : positive := 8;
        end algo_decl;
        scripts/vcu128/makeScoutCaloP2gtProject.sh 0 → 100755
        + 57
        − 0
        View file @ a0b3d623
        #!/bin/bash
        # set -e # Exit on error.
        if [ -f buildToolSetup.sh ]; then
        source buildToolSetup.sh
        fi
        # Check environmental variables
        if [ -z ${XILINX_VIVADO:+x} ]; then
        echo "Xilinx Vivado environment has not been sourced. Exiting."
        exit 1
        else
        echo "Found Xilinx Vivado at" ${XILINX_VIVADO}
        fi
        if [ -z "${BUILD_DIR}" ]; then
        echo "Environment variable BUILD_DIR is unset. Exiting."
        exit 1
        else
        echo "BUILD_DIR is ${BUILD_DIR}"
        fi
        if [ -z "${MP7FW_TAG}" ]; then
        echo "Environment variable MP7FW_TAG is unset. Exiting."
        exit 1
        else
        echo "MP7FW_TAG is ${MP7FW_TAG}"
        fi
        # Generate decoder
        cp boards/vcu128/addrtab/address_table_calo.json boards/vcu128/addrtab/address_table.json
        mkdir -p boards/vcu128/firmware/hdl/
        # Generate PyHAL address table for TCP/HBM logic
        scripts/common/generate_pyhal_addrtab.py --addrpath boards/vcu128/addrtab/pyhal/ --boardname vcu128 --boardtype calop2gt
        mkdir $BUILD_DIR
        pushd $BUILD_DIR
        ipbb init scouting
        mkdir scouting/src/scouting-preprocessor
        pushd scouting/src
        if [ -z ${CI_JOB_TOKEN+x} ]; then
        ipbb add git -b $MP7FW_TAG https://:@gitlab.cern.ch:8443/cms-cactus/firmware/mp7.git
        else
        ipbb add git -b $MP7FW_TAG https://gitlab-ci-token:${CI_JOB_TOKEN}@gitlab.cern.ch/cms-cactus/firmware/mp7.git
        fi
        popd
        pushd scouting/src/scouting-preprocessor
        ln -sf ../../../../projects
        ln -sf ../../../../components
        ln -sf ../../../../boards
        popd
        pushd scouting
        ipbb proj create vivado scouting_build scouting-preprocessor:projects/vcu128/calop2gt top_scouting_calop2gt.dep
        ipbb toolbox check-dep vivado scouting-preprocessor:projects/vcu128/calop2gt top_scouting_calop2gt.dep
        pushd proj/scouting_build/
        ipbb vivado project
        popd
        popd
        0% or .
        You are about to add 0 people to the discussion. Proceed with caution.
        Please register or to comment