Module plotting includes SYNC in TDAC plot

The TDAC distribution plot always shows a very large bin at TDAC 0. From a quick glance, i would guess that only the SYNC FE of the first FE is excluded, while the SYNCs on all following chips are included.

Here is two TDAC distribution plots from a threshold scan on a DC module:

Note: The sum of all 0 TDACs should be around 9000. Here's the resulting module plot:

It has 24000 entries too many in the 0 bin, exacly one SYNC FE ;)