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Speed up chip sim

Merged Mark Standke requested to merge maybe_seed_up into development
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@@ -37,7 +37,7 @@ module tb #(
parameter VERSION_MINOR = 8'd0,
parameter VERSION_PATCH = 8'd0
)(
input wire BUS_CLK,
output reg BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
@@ -62,6 +62,9 @@ localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
initial BUS_CLK = 1'b0;
always #(5000 / 2) BUS_CLK = !BUS_CLK;
// ----- Clock (mimics a PLL) -----
localparam PLL_MUL = 5;
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