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silab
bdaq53
Merge requests
!465
Speed up chip sim
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Merged
Speed up chip sim
maybe_seed_up
into
development
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0
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2
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2
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4
Merged
Mark Standke
requested to merge
maybe_seed_up
into
development
3 years ago
Overview
0
Commits
2
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2
Changes
4
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This MR speeds up chip simulation (approx. 25%) by using a newer basil version.
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0
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development
version 1
33114ca9
3 years ago
development (base)
and
latest version
latest version
58a2223a
2 commits,
3 years ago
version 1
33114ca9
2 commits,
3 years ago
4 files
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10
−
4
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bdaq53/tests/ITkPixV1/hdl/bdaq53_tb.v
+
4
−
1
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@@ -37,7 +37,7 @@ module tb #(
parameter
VERSION_MINOR
=
8'd0
,
parameter
VERSION_PATCH
=
8'd0
)(
in
put
wi
re
BUS_CLK
,
out
put
re
g
BUS_CLK
,
input
wire
BUS_RST
,
input
wire
[
31
:
0
]
BUS_ADD
,
inout
wire
[
31
:
0
]
BUS_DATA
,
@@ -62,6 +62,9 @@ localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam
ABUSWIDTH
=
32
;
assign
BUS_BYTE_ACCESS
=
BUS_ADD
<
32'h8000_0000
?
1'b1
:
1'b0
;
initial
BUS_CLK
=
1'b0
;
always
#(
5000
/
2
)
BUS_CLK
=
!
BUS_CLK
;
// ----- Clock (mimics a PLL) -----
localparam
PLL_MUL
=
5
;
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