DFF output to bit-select of vector is not mappable
Whenever Yosys creates DFFs whose \Q output connects only to single bits of a vector, this can not be back-annotated to a full wire in the yosys design. Calling to_wire() on this SigSpec causes an assertion failure. Even if this could be circumvented, then some simulators could not access individual signal bits and additional logic would need to be put in place.
TODO: Detect this condition and raise a proper error, instead of just assertion-crashing.