Macros for bitwidth not completely supported
Summary
Syntax not supported
Describe your setup
Fastrich
TMRG Version
REPRODUCED_111
Steps to reproduce
module test;
`define W 5
logic [`W-1:0] a;
logic [`W-1:0] b;
wire [`W-1:0] c = a - `W'b001;
endmodule
What is the current bug behavior?
$ tmrg test.sv
[ERROR ] Error in file 'test.sv' around line '6'.
[ERROR ]
[ERROR ] wire [`W-1:0] c = a - `W'b001;
[ERROR ] ^
[ERROR ] Expected module, found 'wire' (at char 87), (line:6, col:3)
[ERROR ] Error during parsing
What is the expected correct behavior?
Triplication working
Possible fixes
To be investigated