generate if/else without begin/end does not get triplicated correctly
Summary
generate if/else does not get triplicated correctly
Describe your setup
mosaix
TMRG Version
REPRODUCED_136
Steps to reproduce
module dut;
logic a, b, c;
generate
if (1'b1)
assign a = b;
else
assign a = c;
endgenerate
endmodule
What is the current bug behavior?
module dutTMR;
logic aA;
logic aB;
logic aC;
logic bA;
logic bB;
logic bC;
logic cA;
logic cB;
logic cC;
generate
if (1'b1)
assign aA = bA;
else
assign aB = bB;
endgenerate
endmodule
What is the expected correct behavior?
module dutTMR;
logic aA;
logic aB;
logic aC;
logic bA;
logic bB;
logic bC;
logic cA;
logic cB;
logic cC;
generate
if (1'b1) begin
assign aA = bA;
assign aB = bB;
assign aC = bC;
end else begin
assign aA = cA;
assign aB = cB;
assign aC = cC;
end
endgenerate
endmodule
Possible fixes
PATCH: wrapping the if/else statements inside a begin end patches the issue