Unpacked arrays declaration changed in tbg
Summary
tbg
is now changing the definition of unpacked arrays
Describe your setup
ECON, common aligner
TMRG Version
running release tmrg_v1.1.0
at tag REPRODUCED_81
Steps to reproduce
tbg test.sv
with test.sv
module a (
output logic b[2]
);
endmodule
What is the current bug behavior?
The testbench generated has a different definition for the signal used to assign b
.
wire bA [0 : 1];
wire bB [0 : 1];
wire bC [0 : 1];
NOTE: the order is maintained!
What is the expected correct behavior?
The testbench generated has the same definition for the signal used to assign b
.
wire bA [2];
wire bB [2];
wire bC [2];
NOTE: the issue was difficult to visualise during testing due to the high number of spaces added before and after the :
in the range definition.