Feed single PF IP core from 36 links
In #11 (closed) the logic was changed to provide the PF algorithm with the expected 72 32 bit words per 240 MHz tick. This was done by sending the set of all 32 bit words received by the 72 input links to one IP core and cycle through six identical IP cores for each of the six frames received during a LHC bunch crossing (in #11 (closed) only one such IP core was instantiated with 5/6 of the data being ignored).
The above described construction leads to timing problems, so we should try to use only 36 per IP core and use the second arriving word of each link. This means that the word that arrives first needs to be delayed by one tick. The link -> PF input mapping would look something like this:
d0, f0 -> pfD0 d0, f1 -> pfD1 d1, f0 -> pfD2 d1, f1 -> pfD3 [...] d35, f0 -> pfD70 d35, f1 -> pfD71
In the target FPGA this would mean that the first N/2 IP cores were supplied by the first M/2 links while the second N/2 IP cores would receive data from the second half of input links.