Skip to content
Snippets Groups Projects
Commit 738e6971 authored by Frans Schreuder's avatar Frans Schreuder
Browse files

Regenerated latex

parent 2e7697d0
No related branches found
No related tags found
1 merge request!308Added license headers (Apache v2)
Pipeline #3287288 failed
Stage: sim
    Stage: build_full_4ch
      Stage: build_gbt_4ch
        Stage: build_strip_4ch
          Stage: build_pixel_4ch
            Stage: build_lpgbt_4ch
              Expand all Hide whitespace changes
              Inline Side-by-side
              sources/templates/build-doc.sh
              + 1
              − 0
              View file @ 738e6971
              ...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
              # build the documentation from the registermap.tex file # build the documentation from the registermap.tex file
              firmware_dir=../.. firmware_dir=../..
              wuppercodegen_dir=$firmware_dir/WupperCodeGen wuppercodegen_dir=$firmware_dir/WupperCodeGen
              wuppercodegen=$wuppercodegen_dir/wuppercodegen/cli.py
              registers=registers-5.0.yaml registers=registers-5.0.yaml
              $wuppercodegen --version $wuppercodegen --version
              $wuppercodegen $registers registermap.tex.template registermap-5.0.tex $wuppercodegen $registers registermap.tex.template registermap-5.0.tex
              ......
              sources/templates/registermap-5.0.tex
              + 88
              − 46
              View file @ 738e6971
              ...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
              % by the script 'wuppercodegen', version: 0.8.4, % by the script 'wuppercodegen', version: 0.8.4,
              % using the following commandline: % using the following commandline:
              % %
              % ../../../software/wuppercodegen/wuppercodegen/cli.py registers-5.0.yaml registermap.tex.template registermap-5.0.tex % ../../WupperCodeGen/wuppercodegen/cli.py registers-5.0.yaml registermap.tex.template registermap-5.0.tex
              % %
              % Please do NOT edit this file, but edit the source file at 'registermap.tex.template' % Please do NOT edit this file, but edit the source file at 'registermap.tex.template'
              % %
              ...@@ -229,28 +229,30 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA ...@@ -229,28 +229,30 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
              \hline \hline
              0x0100 & 0,1 & \multicolumn{4}{c|}{\small INCLUDE\_EGROUP\_0} \\ 0x0100 & 0,1 & \multicolumn{4}{c|}{\small INCLUDE\_EGROUP\_0} \\
              \cline{3-6} \cline{3-6}
              & & FROMHOST\_02 & 8 & R & FromHost EPROC02 is included in this EGROUP \\ & & TOHOST\_32 & 9 & R & ToHost EPATH32 is included in this EGROUP \\
              & & FROMHOST\_04 & 7 & R & FromHost EPROC04 is included in this EGROUP \\ & & FROMHOST\_02 & 8 & R & FromHost EPATH02 is included in this EGROUP \\
              & & FROMHOST\_08 & 6 & R & FromHost EPROC8 is included in this EGROUP \\ & & FROMHOST\_04 & 7 & R & FromHost EPATH04 is included in this EGROUP \\
              & & FROMHOST\_08 & 6 & R & FromHost EPATH8 is included in this EGROUP \\
              & & FROMHOST\_HDLC & 5 & R & FromHost HDLC is included in this EGROUP \\ & & FROMHOST\_HDLC & 5 & R & FromHost HDLC is included in this EGROUP \\
              & & TOHOST\_02 & 4 & R & ToHost EPROC02 is included in this EGROUP \\ & & TOHOST\_02 & 4 & R & ToHost EPATH02 is included in this EGROUP \\
              & & TOHOST\_04 & 3 & R & ToHost EPROC04 is included in this EGROUP \\ & & TOHOST\_04 & 3 & R & ToHost EPATH04 is included in this EGROUP \\
              & & TOHOST\_08 & 2 & R & ToHost EPROC08 is included in this EGROUP \\ & & TOHOST\_08 & 2 & R & ToHost EPATH08 is included in this EGROUP \\
              & & TOHOST\_16 & 1 & R & ToHost EPROC16 is included in this EGROUP \\ & & TOHOST\_16 & 1 & R & ToHost EPATH16 is included in this EGROUP \\
              & & TOHOST\_HDLC & 0 & R & ToHost HDLC is included in this EGROUP \\ & & TOHOST\_HDLC & 0 & R & ToHost HDLC is included in this EGROUP \\
              \hline \hline
              \multicolumn{6}{|c|}{\ldots} \\ \multicolumn{6}{|c|}{\ldots} \\
              \hline \hline
              0x0160 & 0,1 & \multicolumn{4}{c|}{\small INCLUDE\_EGROUP\_6} \\ 0x0160 & 0,1 & \multicolumn{4}{c|}{\small INCLUDE\_EGROUP\_6} \\
              \cline{3-6} \cline{3-6}
              & & FROMHOST\_02 & 8 & R & FromHost EPROC02 is included in this EGROUP \\ & & TOHOST\_32 & 9 & R & ToHost EPATH32 is included in this EGROUP \\
              & & FROMHOST\_04 & 7 & R & FromHost EPROC04 is included in this EGROUP \\ & & FROMHOST\_02 & 8 & R & FromHost EPATH02 is included in this EGROUP \\
              & & FROMHOST\_08 & 6 & R & FromHost EPROC8 is included in this EGROUP \\ & & FROMHOST\_04 & 7 & R & FromHost EPATH04 is included in this EGROUP \\
              & & FROMHOST\_08 & 6 & R & FromHost EPATH8 is included in this EGROUP \\
              & & FROMHOST\_HDLC & 5 & R & FromHost HDLC is included in this EGROUP \\ & & FROMHOST\_HDLC & 5 & R & FromHost HDLC is included in this EGROUP \\
              & & TOHOST\_02 & 4 & R & ToHost EPROC02 is included in this EGROUP \\ & & TOHOST\_02 & 4 & R & ToHost EPATH02 is included in this EGROUP \\
              & & TOHOST\_04 & 3 & R & ToHost EPROC04 is included in this EGROUP \\ & & TOHOST\_04 & 3 & R & ToHost EPATH04 is included in this EGROUP \\
              & & TOHOST\_08 & 2 & R & ToHost EPROC08 is included in this EGROUP \\ & & TOHOST\_08 & 2 & R & ToHost EPATH08 is included in this EGROUP \\
              & & TOHOST\_16 & 1 & R & ToHost EPROC16 is included in this EGROUP \\ & & TOHOST\_16 & 1 & R & ToHost EPATH16 is included in this EGROUP \\
              & & TOHOST\_HDLC & 0 & R & ToHost HDLC is included in this EGROUP \\ & & TOHOST\_HDLC & 0 & R & ToHost HDLC is included in this EGROUP \\
              \hline \hline
              0x0170 & 0,1 & WIDE\_MODE & 0x0170 & 0,1 & WIDE\_MODE &
              ...@@ -377,21 +379,23 @@ any & T & Central Router FromHost Controls and Monitors \\ ...@@ -377,21 +379,23 @@ any & T & Central Router FromHost Controls and Monitors \\
              \hline \hline
              0x2300 & 0,1 & \multicolumn{4}{c|}{\small DECODING\_LINK00\_EGROUP0\_CTRL} \\ 0x2300 & 0,1 & \multicolumn{4}{c|}{\small DECODING\_LINK00\_EGROUP0\_CTRL} \\
              \cline{3-6} \cline{3-6}
              & & ENABLE\_TRUNCATION & 59 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
              & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\ & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
              & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\ & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
              & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\ & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
              & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\ & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
              & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\ & & EPATH\_ENA & 7:0 & W & Enable bits per EPATH \\
              \hline \hline
              \multicolumn{6}{|c|}{\ldots} \\ \multicolumn{6}{|c|}{\ldots} \\
              \hline \hline
              0x2360 & 0,1 & \multicolumn{4}{c|}{\small DECODING\_LINK00\_EGROUP6\_CTRL} \\ 0x2360 & 0,1 & \multicolumn{4}{c|}{\small DECODING\_LINK00\_EGROUP6\_CTRL} \\
              \cline{3-6} \cline{3-6}
              & & ENABLE\_TRUNCATION & 59 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
              & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\ & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
              & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\ & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
              & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\ & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
              & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\ & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
              & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\ & & EPATH\_ENA & 7:0 & W & Enable bits per EPATH \\
              \hline \hline
              \multicolumn{6}{|c|}{\ldots} \\ \multicolumn{6}{|c|}{\ldots} \\
              \hline \hline
              ...@@ -399,26 +403,31 @@ any & T & Central Router FromHost Controls and Monitors \\ ...@@ -399,26 +403,31 @@ any & T & Central Router FromHost Controls and Monitors \\
              \hline \hline
              0x27D0 & 0,1 & \multicolumn{4}{c|}{\small DECODING\_LINK11\_EGROUP0\_CTRL} \\ 0x27D0 & 0,1 & \multicolumn{4}{c|}{\small DECODING\_LINK11\_EGROUP0\_CTRL} \\
              \cline{3-6} \cline{3-6}
              & & ENABLE\_TRUNCATION & 59 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
              & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\ & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
              & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\ & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
              & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\ & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
              & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\ & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
              & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\ & & EPATH\_ENA & 7:0 & W & Enable bits per EPATH \\
              \hline \hline
              \multicolumn{6}{|c|}{\ldots} \\ \multicolumn{6}{|c|}{\ldots} \\
              \hline \hline
              0x2830 & 0,1 & \multicolumn{4}{c|}{\small DECODING\_LINK11\_EGROUP6\_CTRL} \\ 0x2830 & 0,1 & \multicolumn{4}{c|}{\small DECODING\_LINK11\_EGROUP6\_CTRL} \\
              \cline{3-6} \cline{3-6}
              & & ENABLE\_TRUNCATION & 59 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
              & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\ & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
              & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\ & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
              & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\ & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
              & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\ & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
              & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\ & & EPATH\_ENA & 7:0 & W & Enable bits per EPATH \\
              \hline \hline
              \multicolumn{6}{|c|}{MINI\_EGROUP\_TOHOST\_GEN} \\ \multicolumn{6}{|c|}{MINI\_EGROUP\_TOHOST\_GEN} \\
              \hline \hline
              0x2840 & 0,1 & \multicolumn{4}{c|}{\small MINI\_EGROUP\_TOHOST\_00} \\ 0x2840 & 0,1 & \multicolumn{4}{c|}{\small MINI\_EGROUP\_TOHOST\_00} \\
              \cline{3-6} \cline{3-6}
              & & ENABLE\_AUX\_TRUNCATION & 15 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
              & & ENABLE\_IC\_TRUNCATION & 14 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
              & & ENABLE\_EC\_TRUNCATION & 13 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
              & & AUX\_ALMOST\_FULL & 12 & R & Indicator that the AUX path FIFO is almost full \\ & & AUX\_ALMOST\_FULL & 12 & R & Indicator that the AUX path FIFO is almost full \\
              & & AUX\_BIT\_SWAPPING & 11 & W & 0: two input bits of IC e-link are as documented, 1: two input bits are swapped \\ & & AUX\_BIT\_SWAPPING & 11 & W & 0: two input bits of IC e-link are as documented, 1: two input bits are swapped \\
              & & AUX\_ENABLE & 10 & W & Enables the AUX channel \\ & & AUX\_ENABLE & 10 & W & Enables the AUX channel \\
              ...@@ -434,6 +443,9 @@ any & T & Central Router FromHost Controls and Monitors \\ ...@@ -434,6 +443,9 @@ any & T & Central Router FromHost Controls and Monitors \\
              \hline \hline
              0x29B0 & 0,1 & \multicolumn{4}{c|}{\small MINI\_EGROUP\_TOHOST\_23} \\ 0x29B0 & 0,1 & \multicolumn{4}{c|}{\small MINI\_EGROUP\_TOHOST\_23} \\
              \cline{3-6} \cline{3-6}
              & & ENABLE\_AUX\_TRUNCATION & 15 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
              & & ENABLE\_IC\_TRUNCATION & 14 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
              & & ENABLE\_EC\_TRUNCATION & 13 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
              & & AUX\_ALMOST\_FULL & 12 & R & Indicator that the AUX path FIFO is almost full \\ & & AUX\_ALMOST\_FULL & 12 & R & Indicator that the AUX path FIFO is almost full \\
              & & AUX\_BIT\_SWAPPING & 11 & W & 0: two input bits of IC e-link are as documented, 1: two input bits are swapped \\ & & AUX\_BIT\_SWAPPING & 11 & W & 0: two input bits of IC e-link are as documented, 1: two input bits are swapped \\
              & & AUX\_ENABLE & 10 & W & Enables the AUX channel \\ & & AUX\_ENABLE & 10 & W & Enables the AUX channel \\
              ...@@ -451,31 +463,19 @@ any & T & Central Router FromHost Controls and Monitors \\ ...@@ -451,31 +463,19 @@ any & T & Central Router FromHost Controls and Monitors \\
              0x29D0 & 0,1 & DECODING\_REVERSE\_10B & 0x29D0 & 0,1 & DECODING\_REVERSE\_10B &
              0 & W & Reverse 10-bit word of elink data for 8b10b E-links\newline 1: Receive 10-bit word in ToHost E-Paths, MSB first\newline 0: Receive 10-bit word in ToHost E-Paths, LSB first\newline \\ 0 & W & Reverse 10-bit word of elink data for 8b10b E-links\newline 1: Receive 10-bit word in ToHost E-Paths, MSB first\newline 0: Receive 10-bit word in ToHost E-Paths, LSB first\newline \\
              \hline \hline
              \multicolumn{6}{|c|}{YARR\_DEBUG} \\ \multicolumn{6}{|c|}{YARR\_DEBUG\_ALLEGROUP\_TOHOST\_GEN} \\
              \hline \hline
              0x29E0 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_FROMHOST\_00} \\ 0x29E0 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_ALLEGROUP\_TOHOST\_00} \\
              \cline{3-6} \cline{3-6}
              & & RD53A\_AZ\_EN & 56 & W & Auto zeroing module enable \\ & & REF\_PACKET & 63:32 & W & Reference packet to be matched \\
              & & CNT\_TRIG\_CMD & 55:24 & R & Number of issued triggers via cmd \\ & & CNT\_RX\_PACKET & 31:0 & R & Count packets of a given value \\
              & & CNT\_GENCALTRIG\_DLY & 23:16 & R & Measured distance between GenCal and first issued trigger via cmd \\
              & & ERR\_GENCALTRIG\_DLY & 15:8 & R & Number of mismatches between CNT\_GENCALTRIG\_DLY and REF\_DLY\_GENCALTRIG \\
              & & REF\_DLY\_GENCALTRIG & 7:0 & W & Reference distance between GenCal and First Trigger \\
              \hline
              0x29F0 & 0,1 & CNT\_RX\_64B66BHDR\_LANE0\_00 &
              31:0 & R & RD53A HDR from 64b66b module. LANE0 only \\
              \hline \hline
              \multicolumn{6}{|c|}{\ldots} \\ \multicolumn{6}{|c|}{\ldots} \\
              \hline \hline
              0x2B40 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_FROMHOST\_11} \\ 0x2A90 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_ALLEGROUP\_TOHOST\_11} \\
              \cline{3-6} \cline{3-6}
              & & RD53A\_AZ\_EN & 56 & W & Auto zeroing module enable \\ & & REF\_PACKET & 63:32 & W & Reference packet to be matched \\
              & & CNT\_TRIG\_CMD & 55:24 & R & Number of issued triggers via cmd \\ & & CNT\_RX\_PACKET & 31:0 & R & Count packets of a given value \\
              & & CNT\_GENCALTRIG\_DLY & 23:16 & R & Measured distance between GenCal and first issued trigger via cmd \\
              & & ERR\_GENCALTRIG\_DLY & 15:8 & R & Number of mismatches between CNT\_GENCALTRIG\_DLY and REF\_DLY\_GENCALTRIG \\
              & & REF\_DLY\_GENCALTRIG & 7:0 & W & Reference distance between GenCal and First Trigger \\
              \hline
              0x2B50 & 0,1 & CNT\_RX\_64B66BHDR\_LANE0\_11 &
              31:0 & R & RD53A HDR from 64b66b module. LANE0 only \\
              \hline \hline
              \multicolumn{6}{|c|}{SUPER\_CHUNK\_FACTOR\_GEN} \\ \multicolumn{6}{|c|}{SUPER\_CHUNK\_FACTOR\_GEN} \\
              \hline \hline
              ...@@ -646,6 +646,43 @@ any & T & Central Router FromHost Controls and Monitors \\ ...@@ -646,6 +646,43 @@ any & T & Central Router FromHost Controls and Monitors \\
              & & AUTOMATIC\_MERGE\_DISABLE0 & 1 & W & Disable automatic merging \\ & & AUTOMATIC\_MERGE\_DISABLE0 & 1 & W & Disable automatic merging \\
              & & TTC\_SELECT0 & 0 & W & TTC/FromHost select (if automatic merging is disabled) \\ & & TTC\_SELECT0 & 0 & W & TTC/FromHost select (if automatic merging is disabled) \\
              \hline \hline
              \multicolumn{6}{|c|}{YARR\_DEBUG\_ALLEGROUP\_FROMHOST\_GEN} \\
              \hline
              0x3910 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_ALLEGROUP\_FROMHOST1\_00} \\
              \cline{3-6}
              & & RD53A\_AZ\_EN & 48 & W & Auto zeroing module enable \\
              & & CNT\_TRIG\_CMD & 47:16 & R & Number of issued triggers via cmd \\
              & & ERR\_GENCALTRIG\_DLY & 15:8 & R & Number of mismatches between CNT\_GENCALTRIG\_DLY and REF\_DLY\_GENCALTRIG \\
              & & REF\_DLY\_GENCALTRIG & 7:0 & W & Reference distance between GenCal and First Trigger \\
              \hline
              0x3920 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_ALLEGROUP\_FROMHOST2\_00} \\
              \cline{3-6}
              & & CNT\_CMD & 47:16 & R & Number of issued commands \\
              & & REF\_CMD & 15:0 & W & Cmd type to be counted. See RD53 Manual for list of allowed commands \\
              \hline
              \multicolumn{6}{|c|}{\ldots} \\
              \hline
              0x3A70 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_ALLEGROUP\_FROMHOST1\_11} \\
              \cline{3-6}
              & & RD53A\_AZ\_EN & 48 & W & Auto zeroing module enable \\
              & & CNT\_TRIG\_CMD & 47:16 & R & Number of issued triggers via cmd \\
              & & ERR\_GENCALTRIG\_DLY & 15:8 & R & Number of mismatches between CNT\_GENCALTRIG\_DLY and REF\_DLY\_GENCALTRIG \\
              & & REF\_DLY\_GENCALTRIG & 7:0 & W & Reference distance between GenCal and First Trigger \\
              \hline
              0x3A80 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_ALLEGROUP\_FROMHOST2\_11} \\
              \cline{3-6}
              & & CNT\_CMD & 47:16 & R & Number of issued commands \\
              & & REF\_CMD & 15:0 & W & Cmd type to be counted. See RD53 Manual for list of allowed commands \\
              \hline
              0x3A90 & 0,1 & YARR\_FROMHOST\_CALTRIGSEQ\_WE &
              0 & W & enable to store CalPulse+Trigger Sequence into memory \\
              \hline
              0x3AA0 & 0,1 & YARR\_FROMHOST\_CALTRIGSEQ\_WRDATA &
              15:0 & W & CalPulse+Trigger Sequence to be stored in memory \\
              \hline
              0x3AB0 & 0,1 & YARR\_FROMHOST\_CALTRIGSEQ\_WRADDR &
              4:0 & W & memory address to store CalPulse+Trigger Sequence \\
              \hline
              \multicolumn{6}{|c|}{Frontend Emulator Controls And Monitors} \\ \multicolumn{6}{|c|}{Frontend Emulator Controls And Monitors} \\
              \hline \hline
              0x4000 & 0, 1 & \multicolumn{4}{c|}{\small FE\_EMU\_ENA} \\ 0x4000 & 0, 1 & \multicolumn{4}{c|}{\small FE\_EMU\_ENA} \\
              ...@@ -778,6 +815,11 @@ any & T & Central Router FromHost Controls and Monitors \\ ...@@ -778,6 +815,11 @@ any & T & Central Router FromHost Controls and Monitors \\
              & & LOCK & 48 & W & Locks this particular register. If set prevents software from touching it. \\ & & LOCK & 48 & W & Locks this particular register. If set prevents software from touching it. \\
              & & SEL & 47:0 & W & ToFrontEnd FanOut/Selector. Every bitfield is a channel:\newline 1 : GBT\_EMU, select GBT Emulator for a specific GBT link\newline 0 : TTC\_DEC, select CentralRouter data (including TTC) for a specific GBT link\newline \newline \\ & & SEL & 47:0 & W & ToFrontEnd FanOut/Selector. Every bitfield is a channel:\newline 1 : GBT\_EMU, select GBT Emulator for a specific GBT link\newline 0 : TTC\_DEC, select CentralRouter data (including TTC) for a specific GBT link\newline \newline \\
              \hline \hline
              0x5720 & 0 & \multicolumn{4}{c|}{\small FULLMODE\_AUTO\_RX\_RESET} \\
              \cline{3-6}
              & & ENABLE & 32 & W & Enable the Automatic RX Reset mechanism \\
              & & TIMEOUT & 31:0 & W & Number of 40 MHz clock cycles until an unaligned link results in a reset pulse \\
              \hline
              \multicolumn{6}{|c|}{Link Wrapper Monitors} \\ \multicolumn{6}{|c|}{Link Wrapper Monitors} \\
              \hline \hline
              0x6600 & 0 & \multicolumn{4}{c|}{\small GBT\_VERSION} \\ 0x6600 & 0 & \multicolumn{4}{c|}{\small GBT\_VERSION} \\
              ...@@ -948,7 +990,7 @@ any & T & Any write to this register resets the TTC Emulator to the default stat ...@@ -948,7 +990,7 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
              3:0 & W & Controls the low threshold of the channel fifo in FULL mode on which\newline an Xon will be asserted, bitfields control 4 MSB\newline \\ 3:0 & W & Controls the low threshold of the channel fifo in FULL mode on which\newline an Xon will be asserted, bitfields control 4 MSB\newline \\
              \hline \hline
              0x8010 & 0, 1 & XOFF\_FM\_CH\_FIFO\_THRESH\_HIGH & 0x8010 & 0, 1 & XOFF\_FM\_CH\_FIFO\_THRESH\_HIGH &
              3:0 & W & Controls the high threshold of the channel fifo in FULL mode on which\newline an Xoff will be asserted, bitfields control 4 MSB - name: XOFF\_FM\_LOW\_THRESH\_CROSSED\newline \\ 3:0 & W & Controls the high threshold of the channel fifo in FULL mode on which\newline an Xoff will be asserted, bitfields control 4 MSB\newline \\
              \hline \hline
              0x8020 & 0, 1 & XOFF\_FM\_LOW\_THRESH\_CROSSED & 0x8020 & 0, 1 & XOFF\_FM\_LOW\_THRESH\_CROSSED &
              23:0 & R & FIFO filled beyond the low threshold, 1 bit per channel \\ 23:0 & R & FIFO filled beyond the low threshold, 1 bit per channel \\
              ...@@ -1360,8 +1402,8 @@ any & T & Any write to this register clears the FELIG L1ID \\ ...@@ -1360,8 +1402,8 @@ any & T & Any write to this register clears the FELIG L1ID \\
              \hline \hline
              0xB800 & 0 & \multicolumn{4}{c|}{\small FMEMU\_EVENT\_INFO} \\ 0xB800 & 0 & \multicolumn{4}{c|}{\small FMEMU\_EVENT\_INFO} \\
              \cline{3-6} \cline{3-6}
              & & L1ID & 63:32 & W & 32b field to show L1ID \\ & & L1ID & 63:32 & R & 32b field to show L1ID \\
              & & BCID & 31:0 & W & 32b field to show BCID \\ & & BCID & 31:0 & R & 32b field to show BCID \\
              \hline \hline
              0xB810 & 0 & \multicolumn{4}{c|}{\small FMEMU\_COUNTERS} \\ 0xB810 & 0 & \multicolumn{4}{c|}{\small FMEMU\_COUNTERS} \\
              \cline{3-6} \cline{3-6}
              ...@@ -1377,14 +1419,14 @@ any & T & Any write to this register clears the FELIG L1ID \\ ...@@ -1377,14 +1419,14 @@ any & T & Any write to this register clears the FELIG L1ID \\
              & & XONXOFF\_BITNR & 55:48 & W & Bitfield for Xon/Xoff in TTC frame \\ & & XONXOFF\_BITNR & 55:48 & W & Bitfield for Xon/Xoff in TTC frame \\
              & & EMU\_START & 47:47 & W & Start emulator functionality \\ & & EMU\_START & 47:47 & W & Start emulator functionality \\
              & & TTC\_MODE & 46:46 & W & Control the emulator by TTC input or by RegMap (1/0) \\ & & TTC\_MODE & 46:46 & W & Control the emulator by TTC input or by RegMap (1/0) \\
              & & XONXOFF & 45:45 & W & Debug Xon/Xoff functionality (1/0) \\ & & XONXOFF & 45:45 & W & Enable Xon/Xoff functionality (1/0) \\
              & & INLC\_CRC32 & 44:44 & W & 0: No checksum\newline 1: Append the data with a CRC32\newline \\ & & INLC\_CRC32 & 44:44 & W & 0: No checksum\newline 1: Append the data with a CRC32\newline \\
              & & BCR & 43:43 & W & Reset BCID to 0 \\ & & BCR & 43:43 & W & Reset BCID to 0 \\
              & & ECR & 42:42 & W & Reset L1ID to 0 \\ & & ECR & 42:42 & W & Reset L1ID to 0 \\
              & & DATA\_SRC\_SEL & 41:41 & W & Data source select\newline 0: Data input comes from EMURAM\newline 1: Data input comes from PCIe\newline \\ & & CONSTANT\_CHUNK\_LENGTH & 41:41 & W & Data source select\newline 0: Random chunk length\newline 1: Constant chunk length\newline \\
              & & INT\_STATUS\_EMU & 40:32 & R & Read internal status emulator \\ & & INT\_STATUS\_EMU & 40:32 & R & Read internal status emulator \\
              & & FFU\_FM\_EMU\_T & 31:16 & W & For Future Use (trigger registers) \\ & & FFU\_FM\_EMU\_T & 16 & W & For Future Use (trigger registers) \\
              & & FFU\_FM\_EMU\_W & 15:0 & W & For Future Use (write registers) \\ & & FE\_BUSY\_ENABLE & 0 & W & Enable the BUSY mechanism if L1A counter passes threshold \\
              \hline \hline
              0xB830 & 0 & FMEMU\_RANDOM\_RAM\_ADDR & 0xB830 & 0 & FMEMU\_RANDOM\_RAM\_ADDR &
              9:0 & W & Controls the address of the ramblock for the random number generator \\ 9:0 & W & Controls the address of the ramblock for the random number generator \\
              ...@@ -1553,7 +1595,7 @@ any & T & (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 s ...@@ -1553,7 +1595,7 @@ any & T & (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 s
              0xF130 & 0 & MROD\_EP1\_TXRESET & 0xF130 & 0 & MROD\_EP1\_TXRESET &
              23:0 & W & EP1 Transmitter Reset channel 23-0 \\ 23:0 & W & EP1 Transmitter Reset channel 23-0 \\
              \hline \hline
              \multicolumn{6}{|c|}{MROD Monitors} \\ \multicolumn{6}{|c|}{MRO Dmonitors} \\
              \hline \hline
              0xF800 & 0 & MROD\_EP0\_CSMH\_EMPTY & 0xF800 & 0 & MROD\_EP0\_CSMH\_EMPTY &
              23:0 & R & EP0 CSM Handler FIFO Empty 23-0 \\ 23:0 & R & EP0 CSM Handler FIFO Empty 23-0 \\
              ......
              sources/templates/registermap.tex
              + 3
              − 711
              View file @ 738e6971
              This diff is collapsed.
              0% or .
              You are about to add 0 people to the discussion. Proceed with caution.
              Finish editing this message first!
              Please register or to comment