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Updated date
Output the OCR half way the BCR period from the TTC emulator
!378
· created
Jul 12, 2022
by
Frans Schreuder
Merged
updated
Aug 01, 2022
Connected LMK reference clocks and added them to timing constraints
!380
· created
Jul 13, 2022
by
Frans Schreuder
Merged
updated
Jul 14, 2022
FLX-1937: Implemented instant timeout mechanism
!375
· created
Jul 08, 2022
by
Frans Schreuder
Merged
updated
Jul 12, 2022
Resolve FLX-1769 "Phase2/ addgbtforvcu128"
!317
· created
Dec 10, 2021
by
Frans Schreuder
Merged
updated
Jul 11, 2022
Ported changes for FLX-1892 and FLX-1946 to phase2/master
!374
· created
Jul 05, 2022
by
Frans Schreuder
Merged
updated
Jul 07, 2022
Send double BCR immediately on OCR
!373
· created
Jul 04, 2022
by
Frans Schreuder
master
Merged
updated
Jul 06, 2022
Resolve FLX-1892 "Ttc emulator debug"
!364
· created
Jun 07, 2022
by
Frans Schreuder
master
Merged
updated
Jul 06, 2022
changes to laneregistermap. added ila for registers (still need to add .xci to...
!371
· created
Jul 01, 2022
by
Frans Schreuder
Merged
updated
Jul 06, 2022
Added a register to make the HDLC flag for EC E-Links configurable, default:...
!372
· created
Jul 01, 2022
by
Frans Schreuder
Merged
updated
Jul 02, 2022
Added XVC over PCIe for phase2 (Kintex Ultrascale only)
!367
· created
Jun 10, 2022
by
Frans Schreuder
Merged
updated
Jul 01, 2022
FLX-1453 fixed FELIG GBT timing contrains for 24 channels build
!360
· created
Apr 20, 2022
by
Ricardo Luz
Merged
updated
Jul 01, 2022
Fixed a typo in the evencycle_dma bit for DMA_STATUS 3 (the bit from descriptor 2 was assigned)
!370
· created
Jun 28, 2022
by
Frans Schreuder
Merged
updated
Jun 30, 2022
Invalidate the last part of a truncated chunk, instead of creating a bunch of...
!355
· created
Apr 11, 2022
by
Frans Schreuder
master
Merged
updated
Jun 20, 2022
Reverted Versal IP
!366
· created
Jun 08, 2022
by
Frans Schreuder
phase2/FLX-1769_AddGBTForVCU128
Merged
updated
Jun 09, 2022
Added hgtd testbench to encoding_fileset
!362
· created
May 10, 2022
by
Frans Schreuder
Merged
updated
Jun 09, 2022
New fix for FLX-1864: FIFO counter widths should be one bit more than the log2...
!361
· created
May 03, 2022
by
Frans Schreuder
Merged
updated
May 04, 2022
Resolve FLX-1882 "Phase2/ hgtd altiroc fastcmd"
!358
· created
Apr 19, 2022
by
Frans Schreuder
Merged
updated
May 04, 2022
Add endianness control for FULL mode
!357
· created
Apr 14, 2022
by
Frans Schreuder
Merged
1
updated
Apr 19, 2022
Included XOFF mechanism as described in FLX-1827:
!349
· created
Mar 25, 2022
by
Frans Schreuder
Merged
updated
Apr 14, 2022
Fixed counter widths in WupperFifos (See FLX-1864)
!353
· created
Apr 07, 2022
by
Frans Schreuder
Merged
updated
Apr 14, 2022
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