Merge requests · atlas-tdaq-felix / firmware · GitLab

FELIG working into master

!211 · created Nov 14, 2020 by Ricardo Luz master
- Merged
- 2
updated Nov 16, 2020
Resolve FLX-1368 "Phase2/ pexinitforepyc"

!210 · created Nov 13, 2020 by Frans Schreuder
updated Nov 14, 2020
Phase2/merge master

!208 · created Nov 13, 2020 by Frans Schreuder
updated Nov 14, 2020
timingconstraints_lpgbt fix for phase2/master

!203 · created Nov 08, 2020 by Marco Trovato
- Merged
- 6
updated Nov 13, 2020
Resolve FLX-1287 "Phase2/ fullydynamicgbt"

!202 · created Nov 05, 2020 by Frans Schreuder
updated Nov 12, 2020
Resolve FLX-1358 "Mergephase2scriptsandci"

!204 · created Nov 10, 2020 by Frans Schreuder master
updated Nov 11, 2020
Resolve FLX-1339 "Phase2/ fix8b10bencoder"

!201 · created Nov 03, 2020 by Frans Schreuder
updated Nov 04, 2020
Phase2/split gitlab ci jobs

!200 · created Oct 29, 2020 by Frans Schreuder
updated Nov 03, 2020
Minor fix in the HDLC encoder, it was sometimes skipping the first byte

!196 · created Oct 28, 2020 by Frans Schreuder
- Merged
- 3
updated Oct 30, 2020
Resolve FLX-1105 "Bchan emu"

!181 · created Sep 29, 2020 by Alessandra Camplani master
updated Oct 30, 2020
Add 64b66b decoder and RD53 encoder

!194 · created Oct 27, 2020 by Marco Trovato
updated Oct 29, 2020
Resolve FLX-1113 "Phase2/ fixversaldma2"

!199 · created Oct 28, 2020 by Frans Schreuder
updated Oct 29, 2020
Connected soft_reset to the DNA readout module

!193 · created Oct 26, 2020 by Frans Schreuder master
updated Oct 29, 2020
Added 64b66b decoders and RD53 encoders to simulation import scripts and Sigasi import script

!198 · created Oct 28, 2020 by Frans Schreuder phase2/Add64b66bdecoderRD53encoder_cleanup
- Merged
- 9
updated Oct 29, 2020
aclk assignment fix taken from 64b66b branch (Marco Trovato)

!197 · created Oct 28, 2020 by Frans Schreuder
- Merged
- 4
- Approved
updated Oct 28, 2020
Phase2/add verilog support

!195 · created Oct 28, 2020 by Frans Schreuder
updated Oct 28, 2020
Resolve FLX-1315 "Phase2/ fei4bsupport"

!189 · created Oct 16, 2020 by Marius Wensing
- Merged
updated Oct 23, 2020
Phase2/add fei4 b registers

!191 · created Oct 22, 2020 by Frans Schreuder
- Merged
- Approved
updated Oct 22, 2020
Add felix data source sim

!190 · created Oct 19, 2020 by Frans Schreuder
updated Oct 19, 2020
Added check for evencycle_dma != evencycle_pc in DMA_busy.

!178 · created Sep 25, 2020 by Frans Schreuder master
updated Oct 19, 2020

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