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Updated date
Added CI script to build petalinux kernel
!456
· created
Apr 17, 2023
by
Frans Schreuder
Merged
updated
Apr 19, 2023
Update QSPI controller configuration and set default AXI GPIO state
!455
· created
Apr 14, 2023
by
Frans Schreuder
Merged
updated
Apr 15, 2023
Transmit TLP's out of order in Wupper PCIe simulation model to reproduce FLX-2183
!454
· created
Apr 13, 2023
by
Frans Schreuder
Merged
updated
Apr 14, 2023
Don't generate timeout on the last word of a block
!453
· created
Apr 11, 2023
by
Frans Schreuder
Merged
updated
Apr 13, 2023
Added build scripts for all FLX182 flavours (FLX-2174). Replaced FIFO ip from...
!450
· created
Mar 31, 2023
by
Frans Schreuder
Merged
1
updated
Apr 08, 2023
Resolve FLX-2178 FLX182 "Phase2/ use axi i2c"
!451
· created
Apr 06, 2023
by
Frans Schreuder
Merged
updated
Apr 07, 2023
Adding VUnit support
!449
· created
Mar 28, 2023
by
Frans Schreuder
Merged
updated
Apr 05, 2023
Fixed typo in do_implementation_post.tcl as reported in FLX-2167. Also fixed...
!448
· created
Mar 28, 2023
by
Frans Schreuder
Merged
updated
Mar 30, 2023
Applied changes in bit order of LTI frame as reported by Tong in FLX-1537
!442
· created
Mar 07, 2023
by
Frans Schreuder
Merged
updated
Mar 20, 2023
Restored register for detecting SOB/EOB in 8b10b decoder
!444
· created
Mar 13, 2023
by
Frans Schreuder
master
Merged
updated
Mar 20, 2023
Implemented AUTO RX Reset counters for FULL, GBT and lpGBT in phase2
!439
· created
Mar 06, 2023
by
Frans Schreuder
Merged
updated
Mar 20, 2023
Resolve FLX-2045 "Auto rx reset counter"
!440
· created
Mar 07, 2023
by
Frans Schreuder
master
Merged
updated
Mar 20, 2023
Revamped fw_modes in wuppercodegen 0.9.0
!445
· created
Mar 14, 2023
by
Mark Donszelmann
Merged
Approved
updated
Mar 15, 2023
Added a rule to execute VSG, compile_simlib and simulation for either pushes...
!438
· created
Mar 06, 2023
by
Frans Schreuder
Merged
updated
Mar 07, 2023
Imlemented LTI transmitter and Interlaken receiver on FLX182
!423
· created
Jan 25, 2023
by
Frans Schreuder
Merged
updated
Mar 02, 2023
ToHostAxiStreamController was rewritten (toblock process divided into multiple...
!435
· created
Feb 22, 2023
by
Frans Schreuder
Merged
updated
Mar 01, 2023
64b66b module translated to VDHL and UVVM/Modelsim testbench
!428
· created
Feb 04, 2023
by
Marco Trovato
Merged
3
updated
Feb 28, 2023
Resolve FLX-2118
!433
· created
Feb 16, 2023
by
Marius Wensing
Merged
updated
Feb 22, 2023
Replaced \= in comment by /= to aviod unknown escape character in c...
!434
· created
Feb 17, 2023
by
Frans Schreuder
Merged
updated
Feb 18, 2023
Combined registers from phase2/master_FLX-2106_64b66bsimu and...
!432
· created
Feb 15, 2023
by
Frans Schreuder
Merged
2
updated
Feb 17, 2023
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