Add eFEX to phase-1 simulation test

• add eFEXDriver to Lvl1SimulationConfig.py
• change input file of test_trig_mc_v1Dev_L1SimOnly_phase1_build.py to a sample with supercells

for the second part, I wondered if it was worth giving the file an alias, e.g. ttbar_phase1? Question for @rbielski

cc @afaulkne @jkempste

Trigger/TrigValidation/TrigValTools/share/TrigValInputs.json

@@ -56,6 +56,13 @@
             "/cvmfs/atlas-nightlies.cern.ch/repo/data/data-art/TriggerTest/valid1.410000.PowhegPythiaEvtGen_P2012_ttbar_hdamp172p5_nonallhad.merge.RDO.e4993_s3214_r11315/RDO.17533168._000002.pool.root.1"
         ]
     },
+    "ttbar_phase1": {
+        "source": "mc",
+        "format": "RDO",
+        "paths": [
+            "/cvmfs/atlas-nightlies.cern.ch/repo/data/data-art/TriggerTest/valid1.410000.PowhegPythiaEvtGen_P2012_ttbar_hdamp172p5_nonallhad.merge.RDO.e4993_s3214_d1536_tid18795273_00/RDO.18795273._000063.pool.root.1"
+        ]
+    },
     "ttbar_pu80": {
         "source": "mc",
         "format": "RDO",